Hello everyone,
I'm trying to create a layout fro...
# openlanec
Charly Meyer
09/25/2023, 7:55 AMHello everyone,
I'm trying to create a layout from a Verilog file, but there is an error in synthesis. It says, "Problems in 'check-assert'." However, I don't know what it means. Do you have any ideas?
m
Mitch Bailey
09/25/2023, 9:41 AMMy guess is that with the
check -assertLumon2.\clk_outc
Charly Meyer
09/25/2023, 9:44 AMI will check it
Charly Meyer
09/25/2023, 9:45 AMbut on Vivado the synthesis is good
Charly Meyer
09/25/2023, 10:18 AMI delet clk_out but I have an other issue.
m
Mitch Bailey
09/25/2023, 10:34 AMWhat does the log file say?
c
Charly Meyer
09/25/2023, 10:58 AMABC : Error : The network is combinational.
Charly Meyer
09/25/2023, 11:02 AMI saw I can use with this: set ::env(SYNTH_STRATEGY) {DELAY 1}
but it give an error when I lunch with it, I suppose it doesn't like the syntax
m
Mitch Bailey
09/25/2023, 12:11 PMAre you using
config.jsonconfig.tclc
Charly Meyer
09/25/2023, 12:35 PMconfig.tcl,
Charly Meyer
09/25/2023, 12:41 PMI think I forget somthing
Charly Meyer
09/28/2023, 7:25 AMok the issue " The network is combinational." is solved but I have another problems
y
Yatharth Agarwal
12/05/2023, 6:51 PM@Charly Meyer Could you please share the steps you took to get around the error?? Thanks for the help.
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