open-source-silicon.dev

5t_OpAmp.PNG

TestBench.PNG

FromLayout_Output.PNG

OpAmpLayout.PNG

FromSchematic_Output.PNG

ADC.PNG

I created an Op Amp to be used as comparator for an ADC. When I simulated the schematic everything worked fine, but after creating a layout from the schematic for the Op Amp in magic using "import spice" the post layout simulation was not what I expected. I passed LVS and used ext2spice with both cthresh and rthresh set to infinite to generate the post layout netlist. What could be causing these differences in outputs?

Can you share your xschem spice file and your extracted spice file?

High output resistance because of long drain/source drift regions and small metalic contact coverage. Try 1) a multifinger layout for your transistors and 2) covering the whole drain and source contacts. This way you improve the output resistance by limiting source and drain intrinsic resistance and extrinsic resistance due to contact

<@U02A4K5TG5B>:  I don't think he's at the point of doing full R-C extractions.

<@U04MYJ2VDAQ>:  I think the most likely culprit here comes from doing an extraction of the layout and then inserting it back into the same simulation as the schematic.  Often you'll find that the subcircuit definition dumped by schematic capture has a different pin order than the subcircuit definition dumped by layout extraction.  The pins (ports) in the layout can be assigned indexes to make sure they extract in the same order as the schematic.

The best way to check what's going on is to run LVS.  This is a simple circuit and you might think you can eyeball all the devices and connections---and you probably can---but running LVS gives you a good 1:1 comparison that if nothing else will eliminate most of the possible problems and leave you with only a few possibilities for what might be wrong.

OpAmp5T.spice

OpAmp5T_ext.spice

Ok. I’ll look into it and get back to you. ping me if I don’t. :wink:

layout_test.png

testbench.spice

<@U04MYJ2VDAQ>:  Since you provided screenshots and not files, I had to re-create your testbench netlist by hand.  However, I get the same output from ngspice for both of your netlists.

I don’t see any problems in the files you attached, but sometimes the extracted netlist port order does not match the schematic port order. This can cause different simulation results when the extracted netlist is simply swapped with the schematic netlist.

ADC_tb_ext.spice

Thanks, it seems the issue is occurring when I generate the test bench through xschem using a netlist to represent a component instead of a schematic. Do you know what could be causing the test bench to generate differently? Here are my testbenchs one generated using the op amp schematic and the ext one using the Op-Amp netlist.

<@U04MYJ2VDAQ> Is the pin order on the `OpAmp5T` subckt of `OpAmp5T_ext.spice` and `OpAmp5T.spice` the same? If not, you might want to either add properties to the layout pins that order the pins in the way you want or rearrange the pins in the schematic symbol to match the layout (layout defaults to alphabetical, I think). There is a `pinnumber` (I think) property that you can set on the each symbol pin, but I think you can also text edit the `*.sym` file to list the pins in order. Without the pin number property, the output subckt pins are in the same order they appear in the `*.sym` file. For top level subcircuits which don’t have symbols, other processing is probably required.