Hi, after extracting the netlist from an inverter,...
# analog-designv
Vicente Ramirez
09/20/2023, 2:53 PMHi, after extracting the netlist from an inverter, the conections got all messed up, we dont really know why, we ran an lvs with the netlist of the schematic of said inverter and it passed the test. Can anyone help?
Vicente Ramirez
09/20/2023, 2:54 PMThe Nmos is as one would expect, with the In node at the gate, but we have no idea what happened with the nmos
Vicente Ramirez
09/20/2023, 2:54 PMwe are using 5V devices, if thats relevant
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Tim Edwards
09/20/2023, 3:06 PMYou have a deep hierarcy; the labeled pins are not in the same cells as the FET devices. From the netlist, it looks to me like the connections are correct.
Tim Edwards
09/20/2023, 3:07 PMIf you want to force a particular order to the pins, you need to number the pins.
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Vicente Ramirez
09/20/2023, 3:15 PMThanks! I'll look into it
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