Hi,
If there is no clock in a module (full combin...
# openlaneb
Burak Aykenar
09/12/2023, 1:25 PMHi,
If there is no clock in a module (full combinational circuit), what is the proper way to disable operations related to clock in configuration.
openlane gives error when you don't enter clock pin (or port). If I randomly write a signal for clock pin, it enters CTS stage which I don't want.
If I disable RUN_CTS parameter, then does CLOCK_PORT parameter affects anything in the design?
Regards,
v
Vijayan Krishnan
09/12/2023, 1:41 PM"CLOCK_PORT": "","CLOCK_PORT": null,b
Burak Aykenar
09/12/2023, 1:42 PMThanks @Vijayan Krishnan
But I also disable RUN_CTS, which is ok right?
m
Matt Venn
09/13/2023, 1:12 PMI think it won't run cts if there is no clock
b
Burak Aykenar
09/14/2023, 2:27 PMI did not define any clock port or net, I disabled CTS, but there is a port named prog_clk. I saw clock buffers instantiated in the *.nl.v post-impl netlist file with:
sky130_fd_sc_hd__clkbuf_1
sky130_fd_sc_hd__clkbuf4_
I assume openlane automatically defines any port named *clk as clock?
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