Hi all, I'm tring to do post synthesis simulation using results produced by openlane flow. I encountered following warnings and results are not matching with pre-synthesis, I used following commands to execute.Is there any alternative method to do gate level simulation? Please help me figure this.

iverilog fsm_adder.v adder_fsm_tb.v sky130_sram_1kbyte_1rw1r_32x256_8.v sky130_fd_sc_hd.v primitives.v

vvp a.out

gtkwave dump.vcd

Hi, it would be good if you could provide the expected output and the RTL code so that others can help you more easily. From what I can see, you are not using the

FUNCTIONAL

models, but the timing models. These contain specify blocks so that the timings from your hardened design can be back-annotated via an SDF file. Your version of Icarus Verilog does not yet connect the delayed signals from the

$recrem

and

$setuphold

timing checks. Consequently, the output for these cells will be

x

, which may cause your design not to work. You have two options: - Build the newest version of iverilog from here https://github.com/steveicarus/iverilog - Pass

-DFUNCTIONAL

to iverilog so that the functional models are used (backannotation is not possible in this case)

thank you for replying @Leo Moser I'm attaching expected output and RTL code here. First figure is expected output and next one is output I'm getting.

Hi, from your RTL code I see that you have some inferred latches and mix blocking/non-blocking assignments. This could be causing the issues you are seeing. Please make sure you fully understand these issues and revise your design. Preferably use the SystemVerilog features

always_comb

and

always_ff

, these helped me a lot :) If you use those, you need to pass

-g2012

to iverilog for RTL simulation. As a last step, use a linter (Verilator does a good job) to check your RTL code for undesired patterns. I hope this helps!

Thank you @Leo Moser. So is it problem with RTL itself..?

Yes, I think it could be a problem with the RTL code. First you should correct the RTL code to rule out these problems. If the problem persists after you have done the things I suggested, it may be something else.

Okay.I will do that..Thank you.

I recommend you put everything into a git repo along with a makefile. You want to make it as easy as possible for people to try your code.

I will follow your suggestions from next time. Did you use post synthesis file only for simulation..?. Two

fsm_adder

files are here. One is before synthesis and other after synthesis. @Matt Venn

That's why you should make it easy! I probably used the rtl

@Matt Venn Sorry for making it confusing. Can you please look into post synthesis

fsm_adder

this time and figure out problem.