Hi, I see from openlane grid control file that pitch between horizontal and vertical straps is 180 https://github.com/The-OpenROAD-Project/OpenLane/blob/7e5a2e9fb274c0a100b4859a927a[…]9455ff/docs/source/usage/advanced_power_grid_control.md?plain=1 I got warning using area less than 200x200 for hardening macros "Current core area is too small for the power grid settings chosen. The power grid will be scaled down" When I inspect the resulted gds file I see the distance between vertical power straps is a smaller value: I know from the previous experience from open mpw's, this can cause LVS problems. How is the situation now? What can be the solution for hardening macros less than size 200x200? I want to implement a tile-based implementation such as FPGA tiles. I need to harden designs with 120x120, 60x120 sizes for example. If I use 200x200, then I can only fit a very small amount of tiles and the macro area will be sparse of standard logic cells, so lots of area will not be utilized. @Matt Venn I see your tiny tapeout has 160x100 sizing designs. How did you manage to use this size macros? Regards,

you can specify any pdn you want in your submacro. And in the top you can also change it to any value you want. They are in different metal laters (sub macro => end with met4, top macro ends with met5 that connects met4 straps together) Note: This informations is actual for dky130

By default,

user_project_wrapper

has 8 power rails that are repeated both horizontally and vertically. Make sure your pitch is big enough for all 8 with room for routing regular signals too.

@Mitch Bailey @Arman Avetisyan thanks I am trying to harden a macro, I set H/VPITCH to 30, DIE size of the macro as 60-120 and run the flow. I see in layout there are 3 vertical power lines in MET4, 2 seems to be connected to GND (lower contacts for a cell) and 1 VDD (upper contacts for a cell). By the way, I hardened this module forgetting to add power pins in the Verilog file

`ifdef USE_POWER_PINS
    inout vdda1,	// User area 1 3.3V supply
    inout vdda2,	// User area 2 3.3V supply
    inout vssa1,	// User area 1 analog ground
    inout vssa2,	// User area 2 analog ground
    inout vccd1,	// User area 1 1.8V supply
    inout vccd2,	// User area 2 1.8v supply
    inout vssd1,	// User area 1 digital ground
    inout vssd2,	// User area 2 digital ground
`endif

In openlane documentation, in PDN macro level part it is written that I have to add these pins: https://openlane.readthedocs.io/en/latest/usage/advanced_power_grid_control.html#macro-level "Make sure your pitch is big enough for all 8 with room for routing regular signals too" What is the algorithm for choosing enough length pitch? Is 30 enough? How to define?

Your macros probably don’t need all 8 power rails.

What is the algorithm for choosing enough length pitch?

I imagine (rail width + rail space) * 8 + (normal routing width + normal routing space) * how many normal routes. Check the drc rules for rail width and space.

Thanks, By the way in JSON file of the caravel user proj example (which is a hardened macro example) only vccd1 & vssd1 were defined. "VDD_NETS": [ "vccd1" ], "GND_NETS": [ "vssd1" ], Openlane documentation defines:

"VDD_NETS": "vccd1 vccd2 vdda1 cdda2",
    "GND_NETS": "vssd1 vssd2 vssa1 vssa2"

I don’t think that’s necessary.