open-source-silicon.dev

When I'm doing gate level simulations using iverilog my results are not matching with original results. What might be reason..? <@U017X0NM2E7>

Are the results slightly different or entirely different? Have you included the standard cell and macro verilog libraries?

I included sky130_fd_sc_hd.v and sram_macro and primitives. Results are entirely different

fsm_adder.v

primitives.v

sky130_fd_sc_hd.v

adder_fsm_tb.v

sky130_sram_1kbyte_1rw1r_32x256_8.v

Im using following commands to execute in iverilog   Im using following commands to execute in iverilog   `iverilog fsm_adder.v adder_fsm_tb.v sky130_sram_1kbyte_1rw1r_32x256_8.v sky130_fd_sc_hd.v primitives.v`  `vvp a.out`  `gtkwave dump.vcd` 

Screenshot from 2023-09-12 06-22-28.png

I encountered following warnings while doing that. Why is this happening? Please provide a solution for this

You might want to ping the channel again. I’m barely literate in verilog.