hi，everyone，I want to imitate the macro placement of SRAM, and fix the positions of two registers. So, I copied a similar configuration. However, the following file error occurred. PS: When I simply specify the register as a macro unit (without specifying the position), the same error occurs. Does anyone have any suggestions for me? Thank you very much.

1. Your

test.v

file looks very close to a gate level verilog description and not rtl. openlane generally takes rtl as input and maps that to a specific pdk library. Looks like you might be trying to skip a few steps. 2. The

config.json

file has standard libraries defined in

EXTRA_LEFS

,

EXTRA_GDS_FILES

, and

EXTRA_LIBS

. Normally, only data related to user created macros are used here. The library data is pulled in automatically. What are you using as a base configuration?

Yes, I just want to design a long wire and study it. So, to achieve this goal, I imitated the test_sram_macro to fix the register distance. Then, I used the default configuration.

The standard cells you’re using aren’t really macros. That may be what’s causing part of the problem. Also, I didn’t see any placement data long_wire.cfg.

Oh, there might be some format errors here, this is a picture. Then, do you have any suggestions to help me achieve this purpose? Thank you very much.

Looks like your files might have some 2 byte spaces (from the Chinese character set) that may be causing problems. This works for me but there are a lot of fill and decap cells.

{
  "DESIGN_NAME": "long_wire",
  "VERILOG_FILES": "dir::src/*.v",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 11,
  "FP_PDN_VPITCH": 6.7,
  "FP_PDN_HPITCH": 6.7,
  "DESIGN_IS_CORE": true,
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 1000 4000",
  "PL_TARGET_DENSITY": 0.5,
  "MACRO_PLACEMENT_CFG": "dir::long_wire.cfg",
  "RUN_KLAYOUT_XOR": false,
  "RUN_CVC": false,
  "MAGIC_DRC_USE_GDS": false,
  "QUIT_ON_MAGIC_DRC": false
}

Thank you for your suggestion, and this configuration can work, but the

long_wire.cfg

has not taken effect. The distances shown in the image below are not what I intended. Do you have any other suggestions?

Maybe add these to the config.json file

"SYNTH_BUFFER_DIRECT_WIRES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"RSZ_DONT_TOUCH_RX": [ "CLK", "data_in", "data_out", "reg_tx" ],
"PL_ROUTABILITY_DRIVEN": 0,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
"PL_RESIZER_ALLOW_SETUP_VIOS": 0,

These are just guesses. An expert opinion might be needed.

Alright, using MACRO_PLACEMENT_CFG might not be able to control the layout of standard cells. This idea might not work. So, do you have any suggestions on how I can fix the positions of two registers? Thank you all