We are getting out of range warnings/errors from y...
# openlanes
Selim Sandal
09/08/2023, 1:53 AMWe are getting out of range warnings/errors from yosys even though they are in range, can you help us about this?
`/Users/selimsandal/Developer/OneShotNPU/openlane/user_proj_npu/../../verilog/rtl/npu_v.v357 Warning: Identifier
\vectors.register_0' is implicitly declared.m
Mitch Bailey
09/08/2023, 2:29 AMAre
\vectors.register_0verilog/rtl/npu_v.vs
Selim Sandal
09/08/2023, 2:34 AM@Mitch Bailey they are declared like this
logic [255:0] register_0;
logic [255:0] register_1;
logic [255:0] register_2;
logic [255:0] register_3;
Selim Sandal
09/08/2023, 2:35 AMmodule vector_regs #(
parameter WIDTH = 16,
parameter NUM_VECTORS = 4,
parameter VECTOR_SIZE = 16
) (
input logic clk,
input rst,
input [1:0] read_addr,
output logic [WIDTH*VECTOR_SIZE-1:0] read_data, //partial read
input we, //write enable,
input [5:0] write_addr, // [5:4] selects register, [3:0] selects element
input [WIDTH-1:0] write_data, //partial write
input full_we, //full write enable
input [255:0] full_write_data
);
logic [255:0] register_0;
logic [255:0] register_1;
logic [255:0] register_2;
logic [255:0] register_3;
always_ff @(posedge clk) begin
if (we) begin
case (write_addr[5:4])
2'b00: register_0[write_addr[3:0]*WIDTH +: WIDTH] <= write_data;
2'b01: register_1[write_addr[3:0]*WIDTH +: WIDTH] <= write_data;
2'b10: register_2[write_addr[3:0]*WIDTH +: WIDTH] <= write_data;
2'b11: register_3[write_addr[3:0]*WIDTH +: WIDTH] <= write_data;
endcase
end
if (full_we) begin
case (write_addr[5:4])
2'b00: register_0 <= full_write_data;
2'b01: register_1 <= full_write_data;
2'b10: register_2 <= full_write_data;
2'b11: register_3 <= full_write_data;
endcase
end
end
always_comb begin
case (read_addr)
2'b00: read_data = register_0;
2'b01: read_data = register_1;
2'b10: read_data = register_2;
2'b11: read_data = register_3;
default: read_data = 256'b0;
endcase
end
endmodule
here is the full module
m
Mitch Bailey
09/08/2023, 3:10 AMSo when
write_addr[3:0]4'b0000register_0[0 +: 16]register_0[0:-15]register_0[(write_addr[3+0]+1)*WIDTH-1 +: WIDTH]register_0[15:0]s
Selim Sandal
09/08/2023, 7:10 AMThere are no negative numbered errors in the log file
Selim Sandal
09/08/2023, 7:10 AMall assignments are valid but the flow is still stopping
26 Views