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Does anyone have any information about how much bigger the PMOS should be compared to the NMOS? Or do I need to match them experimentally?

Googling `how much bigger should pmos be that nmos` gives a lot of good answers. Above 2.5 seems to be common, but transfer gates tend to have the same size it seems.

I heard about 2, 2.5, 2.7 and 3  . I think it is somewhere around 2.7 actually, but I have the feeling that this isn't a precise value yet, but it feels like nobody cared to produce a very precise answer yet (perhaps because things are too noisy around it anyway?)

Matching delays of inverter stages... Would be nice if the parasitics are loaded and unloaded in the same time...

It was in total more a question, if someone already has practical experience, where that value is roughly...