Hello all, I am trying to generate gds for an eFPGA using Open Lane. The flow is failing due to LVS error. Herewith, I have attached the log file of eFPGA. Kindly share your ideas with me to rectify the LVS violation. Advance thanks.

@Gavaskar K One problem is that the

decap

cells in the layout are not being reduced like those in the netlist. This may be due to a problem in the power grid. You can manually check the final gds to verify that the power grid is connected. The pdn logs may also provide a clue as to the problem. In the future, you probably want to attach the

lvs.report

instead of the

lvs.log

.

Thanks for your response. Hereafter, I will add the report also.

Please just post in one channel. I've already asked you once. You waste people's time by posting the same question in many channels