Hi,
how can you set --bbox-unsup option for Veril...
# openlaneb
Burak Aykenar
08/31/2023, 1:08 PMHi,
how can you set --bbox-unsup option for Verilator? In config.json?
There is an option in configuration.md LINTER_DEFINES https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/reference/configuration.md
I did not understand exactly how to set --bbox-unsup with LINTER_DEFINES
configuration.md
Flow Configuration Variables
This page is the comprehensive manual for user-configurable flow variables
and their default values.
Variables that are defined by the PDK configuration support files and not the
flow itself are listed <./pdk_configuration.md|in this chapter>.
:::{admonition} A couple things to keep in mind
• This is a comprehesive list- there are many variables here you would never
need to touch. If you want just a brief list of variables you should be
The-OpenROAD-Project/OpenLane | Added by GitHub
Burak Aykenar
08/31/2023, 2:23 PMI will appreciate any help on using SKY130 standard cell instantiated designs. I used OpenFPGA framework to generate fabric netlist (Verilog files). I defined SKY130 standard cells in OpenFPGA netlist generation, so actually all the files have SKY130 standard cell instantiations. I included primitives.v and sky130_fd_sc_hd.v files as Verilog files in config file. The linter complains about table endtable constructs in primitives.v, when I set linter off this time Yosys complains about primitive keyword and gives error saying "unexpected TOK_ID".
So, what should be the proper way, or options in config file, when instantiating SKY130 standard cells?
d
donn
08/31/2023, 4:07 PMThere was an update to handle exactly this issue 6 hours ago- are you on the latest version?
b
Burak Aykenar
09/01/2023, 8:07 AMThanks @donn
I see the commit you mentioned in openlane repo, I cloned latest efabless's caravel user project and the tag of openlane there is 2023.07.19, so i think I need to update openlane in caravel user project?
Burak Aykenar
09/01/2023, 8:24 AMI plan to follow these steps, if you know a better, easier way, please let me know:
1) remove openlane with: rm -r dependencies/openlane_src/
2) Change OPENLANE_TAG ?= 2023.07.19 to OPENLANE_TAG ?= 2023.09.01 in files: openlane/Makefile and Makefile
3) install openlane with "make openlane"
Regards,
Burak Aykenar
09/01/2023, 11:02 AMI actually apply these changes in openlane setup
This time Yosys complains about UNIT_DELAY macro in SKY130 primitives files:
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/blackbox.tcl"
1. Executing Verilog-2005 frontend: /home/mbaykenar/Desktop/workspace/openfpga/yfpga-chipignite/openlane/fpga_top/runs/23_09_01_13_59/tmp/synthesis/blackbox/sky130_fd_sc_hd.patched.v
/home/mbaykenar/Desktop/workspace/openfpga/yfpga-chipignite/openlane/fpga_top/runs/23_09_01_13_59/tmp/synthesis/blackbox/sky130_fd_sc_hd.patched.v28405 ERROR: Unimplemented compiler directive or undefined macro `UNIT_DELAY.
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
while executing
"throw_error"
(procedure "try_exec" line 15)
invoked from within
"try_exec yosys -c $::env(SCRIPTS_DIR)/yosys/blackbox.tcl"
(procedure "generate_blackbox_verilog" line 8)
invoked from within
"generate_blackbox_verilog $patched_file $output_file FUNCTIONAL"
(procedure "run_verilator" line 22)
invoked from within
"run_verilator"
(procedure "run_verilator_step" line 3)
invoked from within
"run_verilator_step"} -errorline 1
Burak Aykenar
09/04/2023, 12:18 PMI removed UNIT_DELAY form sky130_fd_sc_hd.v file and add `define NO_PRIMITIVES in primitives.v file to get rid of linter errors
Hope these changes won't affect the synthesis process
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