Hi....while I'm trying to run hierarchical flow for Ripple carry adder I'm getting LVS error . Please help me to remove this error

3 of your macros are not connected to power/ground in the layout.

dut4

is connected, but

dut1

,

dut2

, and

dut3

are not.

Instance: four_bit_adder:dut4              |Instance: dut4                             
  VGND = 126                               |  VGND = 129                               
  VPWR = 126                               |  VPWR = 129                                                        
                                           |                                           
Instance: four_bit_adder:dut3              |Instance: dut3                             
  VGND = 1                                 |  VGND = 129                               
  VPWR = 1                                 |  VPWR = 129                                                            
                                           |                                           
Instance: four_bit_adder:dut2              |Instance: dut2                             
  VGND = 1                                 |  VGND = 129                               
  VPWR = 1                                 |  VPWR = 129                               
                                           |                                           
Instance: four_bit_adder:dut1              |Instance: dut1                             
  VGND = 1                                 |  VGND = 129                               
  VPWR = 1                                 |  VPWR = 129

This may be because the macros are too small to intersect with the power grid. Take a look at the final layout. You might try manually placing the macros with

"MACRO_PLACEMENT_CFG": "dir::/macro.cfg",

to ensure that they intersect with the power grid.

I didn't find any macro.cfg file in RCA_adder folder. Do I need to add it manually..? Or what should I do to remove this error.

I’m not sure what

RCA_adder

folder you’re referring to. Is this part of an online class or tutorial?

First I have generated gds and lef four_bit_adder then I instantiated 4 of these in my top module to create 16 bit adder. My 16 bit adder design is called RCA_adder. Here bb contains four_bit_adder and four_adder contains lef and gds files required for this design.

Here is a sample

macro.cfg

file.

mprj 214 265 N

The first field is the instance name from the gate level verilog.

N

is the orientation. See here.

Okay. Thank you @Mitch Bailey