Hai all, Herewith I have attached the screenshots ...
# openlaneg
Gavaskar K
08/24/2023, 11:04 AMHai all, Herewith I have attached the screenshots of LUT4AB tile running flow and .JSON which is used for eFPGA. Kindly suggest your ideas with me to rectify setup violation. Advance thanks.
v
Vinayaka Karthik
08/24/2023, 2:09 PMplz try this in config.json
"PL_RESIZER_SETUP_SLACK_MARGIN": 2.0,
"GLB_RESIZER_SETUP_SLACK_MARGIN": 2.0,
Simply increse or decrese the value,,according to the slack violated value ..
i hope this may help you
Vinayaka Karthik
08/24/2023, 2:15 PMor increse the clock period
g
Gavaskar K
08/24/2023, 2:16 PMThanks for your valuable reply. I will try it.
👍 1
Gavaskar K
08/25/2023, 11:54 AMgood noon,
Gavaskar K
08/25/2023, 11:55 AM31-rcx_sta.max.rpt
Gavaskar K
08/25/2023, 11:57 AMI ran the design as per your suggestion. But it doesnot work for me. I attached the file for your reference. Kindly check it in your free time and let me know if there is any possibility for clear the setup violation.
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Vinayaka Karthik
08/25/2023, 4:53 PMtry increase or descreses those config variable by around 20 or
increment or decrement the clk period by 20..
this is what i know,amd how i fixed setup or hold violations in design
g
Gavaskar K
08/25/2023, 4:54 PMok. Thank you.
v
Vinayaka Karthik
08/25/2023, 4:58 PMno thanks
try different combinations of values for those variables ...if still it doesnt work
g
Gavaskar K
08/25/2023, 5:07 PMI tried with various combinations. Still facing the same challenge
v
Vinayaka Karthik
08/25/2023, 5:19 PMokay,,i told to increse by 20 ns in USERCLK as the differece was around 20.
g
Gavaskar K
08/30/2023, 9:12 AMok.
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