Hi all, noob here! I'm uncertain if sky130 allows non-volatile memory. Some sources suggest RRAM, some SONOS flash - can anyone clarify? https://sky130-fd-pr-reram.readthedocs.io/en/latest/background.html https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#sonos-cells Its for a test project, for which I only need 1 bit NVM.

The sky130B process includes RRAM, but sky130A does not. The shuttles may be running split lots - some wafers with sky130A, some with sky130B. I don’t think I’ve seen any designs using SONOS, but then again caravel/caravan doesn’t natively support the exotic voltages needed for flash write/erase.

Thanks @Mitch Bailey ! Where can I find a general overview of whats available for sky130* ?

I’m not an authority, but the links you posted seem to be definitive. Again, the efabless harnesses, caravel and caravan, natively only have 1.8V and 3.3V so that limits the device selection somewhat. The caravan harness does have 11 I/O pads that are not connected to anything, so I assume it is possible to connect these to the external voltage sources required for flash program/erase or the higher voltage devices. Creating internal voltage generators is probably also possible, but outside the digital realm.

Okay, thanks. There's little mentioning of sky130A or sky130B I can find, like: https://isn.ucsd.edu/courses/beng207/lectures/Tim_Edwards_2021_slides.pdf Maybe its just common knowledge and evident when you go through the design flow.

If i.e. you were doing chipignite (or even Matt Venn's TinyTapeout? 🙂 ), what would the process actually look like to ensure that you get put on a wafer with the appropriate process? How does RRAM even integrate into the open-source design flow (you don't have to be using the proprietary version of the PDK, right?)

@Henrik Sørensen: The ChipIgnite runs usually don't support ReRAM but I expect there will be more in the future because there is some active design work being done by teams like OpenRAM at UCSC and others. The SONOS has always been available but SkyWater only open-sourced the basic DRC rules for the device and didn't open-source any IP around the non-volatile RAM. Some people have experimented with this but I am not aware of any results yet. There are devices that support up to 20V which should be possible to produce with a bucket brigade architecture.

thanks.

@Andrew Wright: That's right. The gate does not connect directly to any source of leakage (i.e., diffusion) but is capacitively coupled to circuits around it. It is programmed through hot carrier injection. It is essentially the same thing as SONOS, except that SONOS is a buried layer that couples to the gate directly above it, so it is much more space-efficient, and the buried layer and oxide thicknesses are optimized for the hot carrier injection.

Thanks for all the valuable response. Seems I need to get my feet more wet to really understand how to get my 1-bit NVM.

@Tim Edwards You may have replied to the wrong Andrew above.

@Andrew Wright: Whoops, yes, typical Slack slip.

@Tim Edwards (Anybody know how they are implementing the control gate for programming and erase field control? Usually EE Flash has a floating gate between the control gate and channel.) . There is a nice advertizing page from a vendor describing the topic that can be found by googling "SONOS eFLASH".

@Andrew Wright: If you're asking about what Jennifer Hasler's group is doing, the floating gate is just an unconnected poly gate and covers two devices, one of which is the memory device and the other of which is the programming device. They have numerous papers on the technique, which goes way back to the time that Jen was a student of Carver Mead at his Neuromorphic VLSI lab at Caltech.