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Hello, I want to ask a question about the usage of S130 io library. Dose it contain a designed pin to break the power ring enabling dual VDD/GND on the same padframe?

<@U03JSKFF5PH> As far as I’ve seen, there is nothing in the I/O ring where vccd1 can be shorted to vccd2 or vdda1 can be shorted to vdda2 (nothing for vssd1-vssd2, vssa1-vssa2 combinations either). I have seen user designs that intentionally short those nets in the user project though. <@U016EM8L91B> can probably give a definitive error.

<@U03JSKFF5PH>:  There is a limit to how much the voltages can be broken up around the padframe;  especially as all of the GPIO pads around the frame can be connected to either the user project or the management SoC, they all have to be powered in either mode.  So most of the I/O is running on the VDDIO/VSSIO domain (3.3V) and the VCCD/VSSD domain (1.8V).  Since the VCCD/VSSD buses have to be continous around the whole padframe, the user project domains VCCD1/VSSD1 and VCCD2/VSSD2 have to be routed inside the padframe, and there is no need to cut the buses for them.  The VDDA1/VSSA1 and VDDA2/VSSA2 domains, however, do not have any such restriction, so they are cut by bus dividers in three places on the bottom left, bottom right, and top center, chopping the padframe VDDA/VSSA ring into three parts.  The cell that cuts the buses is a custom cell that I designed called `sky130_ef_io__disconnect_vdda_slice_5um`.

thank you very much. I am looking into it now

S130_padframe_2half_connected_vssd.pptx

Hi <@U016EM8L91B>, thank you again for your help. It is very hard for me to understand all of VDD and VSS buses on the frame. I want to have a dual VDD frame, one is 1.8V and another one is 5V. So I designed the padframe with two 10um broken gaps with only VSSD connected by metal 4 and metal 5 as the global ground. Does this design make any sense from your perspective?

Putting a clean break through the padframe rings is likely to cause ESD issues if not an outright rejection from the foundry.  The pad cells already support both 1.8V (VCCD/VSSD) and 5.0V (VDDA/VSSA) domains, and there are specific power/ground pads for each of those.  So you should not have any need to break the padframe power rings.

Thank you very much. How can I select the power bus connection for each power pad? Is there any documentation that describes this? And is there anything needs to be changed in the analog IO pads? I checked the schematic, it seems most of the power ring are isolated from the circuit of the IO

Hi Tim, I still have the question about the selection of the types of the power/ground pads, I am currently using V2.1.302 version of the PDK. Could you please give me the names of power/ground for both 1.8V(VCCD/VSSD) and 5.0V(VDDA/VSSA) domains, so I can quickly set it up in cadence and test it.

The 1.8V domains available to the user project are  `vccd1/vssd1` and `vccd2/vssd2` .  The 3.3V domains are `vdda1/vssa1` and `vdda2/vssa2`.  There are top-level pins that duplicate the vdda1 domain that have to have different names because they are effectively isolated;  I don't know if that makes a difference to what you need to enter but those names are `vdda1_2/vssa1_2` .
The rest of the domains belong to the management SoC :  `vccd/vssd` (1.8V), `vdda/vssa` (3.3V), and `vddio/vssio` (3.3V).  Again, there are additional pads for the vddio domain called `vddio_2/vssio_2`.
Let me know if you need any additional information.