Recently, there is a strange problem. We cannot define any port "reset" in our macro(IP). There is no issue during hardening of the macro. But at the the time of instantiating it in user_project_wrapper.v the error comes. make user_project_wrapper --> /home/<user>/projects/chipignite/openlane/user_project_wrapper/../../verilog/rtl/my_ip.v19 ERROR: Module port `\reset' is not declared in module header.

which OpenLane tag used? Is

reset

not declared in

user_prject_wrapper.v

?

OpenLane a35b64aa200c91e9eb7dde56db787d6b4c0ea12a

caravel wrapper has following ports

input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

How you're connecting to

reset

? is that

wb_rst_i

?

yes In the instantiation .reset(rst) ... the rst is connected to wb_rst_i

What’s the module definition of

my_ip

? Specifically, what ports are defined? Are you able to share your design hierarchy? Does the verilog hierarchy match the layout or has the verilog been flattened during synthesis?

This is the definition module my_ip ( `ifdef USE_POWER_PINS vccd1, vssd1, `endif reset, clock_in, load, ... .... ); If i rename the pin "reset" to something else then there is no issue during instantiation in user_project_wrapper.

What step generates the error?

Yosys

@Matt Venn Can you tag the yosys people so that they can look into this?

the first thing they will ask is where is the source