does the linter also checks for verilog files included in the blackbox? We have openram memories that have delay and hold timing constructs. Verilator is complaining:

[ERROR]: Timing constructs found in the RTL. Please remove them or wrap them around an ifdef. It heavily unrecommended to rely on timing constructs for synthesis.
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_verilator" line 50)
    invoked from within
"run_verilator"
    (procedure "run_verilator_step" line 3)
    invoked from within
"run_verilator_step"} -errorline 1

I submitted a bug for this in our class last quarter: https://github.com/The-OpenROAD-Project/OpenLane/pull/1836

I see the issue closed by @donn however, I still get this. I don't see the reason for checking synthesis related constructs on blackbox verilog files.

Can you confirm the option is still there and did not get removed?

I still see this error message in the log file:

%Error-NEEDTIMINGOPT: /home/hadirkhan/chipignite/openram_testchip2/openlane/user_project_wrapper/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v:57:5: Use --timing or --no-timing to specify how delays should be handled
                                                                                                                                                           : ... In instance user_project_wrapper.SRAM2.bank1
   57 |     #(T_HOLD) dout0 = 32'bx;

@Hadir Khan look at the commit and see if the --timing argument is still given to verilator.

@Matthew Guthaus did it work for you students before? I see verilator called like this:

try_exec bash -c "verilator \
        --lint-only \
        -Wall \
        --Wno-DECLFILENAME \
        --top-module $::env(DESIGN_NAME) \
        $arg_list"

The option has been removed then. It did work when the option is added.

@Matthew Guthaus I think you meant this option: https://github.com/The-OpenROAD-Project/OpenLane/pull/1837/commits/b8daf502623e5410079bb88132709ce20f686c3a

I made a PR that added "--timing" to verilator.

So far we completely disallow timing constructs. You can also see the following message printed

Timing constructs found in the RTL. Please remove them or wrap them around an ifdef. It heavily unrecommended to rely on timing constructs for synthesis.

@Kareem Farid what about black-box files?

For now they are fully included to avoid undefined module errors. We are looking at other solutions

Oooh right now I remember The key issue is Verilator does not “blackbox” modules— and not importing them would cause “module not found” errors

alright 👍

@Hadir Khan Just to confirm, you should still run lint checking for other things but disable the timing by giving verilator the --timing option.

Yes that’s what I am doing. I’m replicating your PR