HI, Does anyone know what the error is due to in the LVS, read the pins in both files, try flattening and neither

Looks like your schematic buses are all shorted in the layout. eg. schematic

XC1[3] Fin net2[3] sky130_fd_pr__cap_mim_m3_1 W=30 L=23.42 MF=1 m=1
XC1[2] Fin net2[2] sky130_fd_pr__cap_mim_m3_1 W=30 L=23.42 MF=1 m=1
XC1[1] Fin net2[1] sky130_fd_pr__cap_mim_m3_1 W=30 L=23.42 MF=1 m=1
XC1[0] Fin net2[0] sky130_fd_pr__cap_mim_m3_1 W=30 L=23.42 MF=1 m=1

Layout

X28 Fin m3_9990_43600# sky130_fd_pr__cap_mim_m3_1 l=2.342e+07u w=3e+07u
X31 Fin m3_9990_43600# sky130_fd_pr__cap_mim_m3_1 l=2.342e+07u w=3e+07u
X6 Fin m3_9990_43600# sky130_fd_pr__cap_mim_m3_1 l=2.342e+07u w=3e+07u
X9 Fin m3_9990_43600# sky130_fd_pr__cap_mim_m3_1 l=2.342e+07u w=3e+07u

cap_mim

devices are only reduced in parallel.

In connections like the one shown in picture xschem creates 4 distinct nets between C1[3:0] and C2[3:0]. If this is not desired and you want to short together the capacitors place a unique label on the net.

I don't understand the difference, since they are connected, there shouldn't be the same 4 capacitor connections from home, which in the end will generate individual parallels?

The capacitor arrangments shown in picture are different. The first should not match the second. If you don't set a label on the center net xschem assumes netxxx[3:0], so 4 different nets.