@Tim Edwards It seems that netgen will match an empty verilog module to any layout (with an equivalent name) without a black-box warning.

Flattening unmatched subcell T6_ZC_BGR in circuit T6_ZC_BGR_Top (0)(1 instance)
Flattening unmatched subcell T6_ZC_PDN in circuit T6_ZC_BGR_Top (0)(1 instance)
Flattening unmatched subcell T6_ZC_M1_M2_M3 in circuit T6_ZC_BGR_Top (0)(2 instances)
Flattening unmatched subcell T6_ZC_M4_5_6_7_15_14_18_17 in circuit T6_ZC_BGR_Top (0)(1 instance)
Flattening unmatched subcell T6_ZC_sky130_pnp_05v5_W3p40L3p40 in circuit T6_ZC_BGR_Top (0)(1 instance)
Flattening unmatched subcell T6_ZC_pmos_mirror in circuit T6_ZC_BGR_Top (0)(1 instance)

Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_1242_1630#
Cell T6_ZC_BGR_Top (0) disconnected node: m1_n2696_678#
Cell T6_ZC_BGR_Top (0) disconnected node: m2_n2696_678#
Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_1/a_1040_1882#
Cell T6_ZC_BGR_Top (0) disconnected node: m3_n2696_678#
Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_2530_1636#
Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_0/a_1040_1882#
Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_0/a_n2684_3748#
Cell T6_ZC_BGR_Top (0) disconnected node: T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_n66_1638#
Class T6_ZC_BGR_Top (0):  Merged 3 parallel devices.

Subcircuit pins:
Circuit 1: T6_ZC_BGR_Top                                                          |Circuit 2: BGR_Top
----------------------------------------------------------------------------------|----------------------------------------------------------------------------------
(no matching pin)                                                                 |vssa1
(no matching pin)                                                                 |vssa2
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_1242_1630#                 |(no matching pin)
m1_n2696_678#                                                                     |(no matching pin)
m2_n2696_678#                                                                     |(no matching pin)
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_1/a_1040_1882#                             |(no matching pin)
m3_n2696_678#                                                                     |(no matching pin)
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_2530_1636#                 |(no matching pin)
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_0/a_1040_1882#                             |(no matching pin)
T6_ZC_BGR_0/VDD                                                                   |(no matching pin)
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M1_M2_M3_0/a_n2684_3748#                            |(no matching pin)
T6_ZC_BGR_0/T6_ZC_PDN_0/T6_ZC_M4_5_6_7_15_14_18_17_0/a_n66_1638#                  |(no matching pin)
T6_ZC_BGR_0/GND                                                                   |(no matching pin)
T6_ZC_BGR_0/VBGP                                                                  |(no matching pin)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes T6_ZC_BGR_Top and BGR_Top are equivalent.

That's the intended behavior but I would agree that a warning is warranted.