open-source-silicon.dev

In openram , during read operation, by how much the bit line is discharged before the sense amplifier is being enabled?

This is generated by a replica bitline that discharges at 2x the rate of a regular bitline. There are two replica bitcells pulling down during an access.

And replica bitline will be discharged till zero.??

Also , for SRAM memory cell using sky130.  Is there any reason why these special transistors were used? Like nfet_latch ,nfet_pass etc?

yes, they are optically downsized cells footprints. They layout wise are smaller than regular transistors, but have fixed layouts

It will be discharged to zero, but the sense amp will be enabled at the switching point of an inverter.

I didn't design the bitcells, they came directly from Skywater.