Hello everyone, I start to experiment with SRAM memories given by sky130A PDK, when i harden the "sky130_sram_1kbyte_1rw1r_8x1024_8.v" with an interface to work as a FIFO i had some LVS errors. Those errors are strange due to there aren't "vssd1_uq0" and "vccd1_uq0" in the design but those signals apears in the LVS report as (no matching pin). Attach verilog files, config.file, and LVS log reports. Thanks in advance.

LVS in the openlane flow is abstracted LVS, so all the standard cells and sram macros are compared as black boxes. This means that the ports have to match exactly. Your sram layout and verilog have one signal that’s slightly different.

(no matching pin)                          |wmask0                                     
wmask0[0]                                  |(no matching pin)

I suggest modifying the verilog stub. If magic can’t find a connection between two or more layout nets with the same text, it add the suffix

_uq*

to the net name. This is where your

vssd1_uq0

and

vccd1_uq0

come from. If possible, just use one text for each net in the layout.

Well i can fix the LVS error but probably is not the best way, i change the wmask0 input to work with two bits . "input [1:0] wmask0" and i just uses the wmask0[0] wire, How good or bad is that? That was the only way that i found to the signal wmask0 appears in the netlist as wmask0[0].

@Emilio Baungarten Can you share the exact changes that you made to get this to work? What did your sram interface become? @ANKI REDDY SAI PRAVEEN

@Emilio Baungarten Please do share changes you made. I got struck at this problem. It will be helpful for me.

This change is just for the 8x1028 SRAM because it don't use more than one bit mask, to avoid the mismatch in LVS change the parameter

NUM_WMASKS

from

1

to

2

.

parameter = NUM_WMASKS = 2;

Then specify the use of the bit 0 e.g.

if(wmask0_reg[0])