Hello, I tried to include an SRAM macro into a RISC-V core. when I hardened the sram macro results i...

Pavan Mantri

06/15/2023, 10:55 AM

Hello, I tried to include an SRAM macro into a RISC-V core. when I hardened the sram macro results in LVS errors. Attaching the files. Thanks in advance.

38-lvs.lef.log 38-vsdmemsoc.lef.lvs.json vsdmemsoc.v 38-vsdmemsoc.lef.lvs.log sky130_sram_1kbyte_1rw1r_32x256_8.v

Mitch Bailey

06/15/2023, 3:15 PM

@Pavan Mantri From the following lines in the

lvs.log

file

Copy code

Circuit 1: vsdmemsoc                       |Circuit 2: vsdmemsoc
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__fill_1 (6903->203)        |sky130_fd_sc_hd__fill_1 (6903->1) **Mismat
sky130_fd_sc_hd__decap_6 (4481->203)       |sky130_fd_sc_hd__decap_6 (4481->1) **Misma
sky130_ef_sc_hd__decap_12 (19424->203)     |sky130_ef_sc_hd__decap_12 (19424->1) **Mis
...
sky130_fd_sc_hd__decap_3 (2727->203)       |sky130_fd_sc_hd__decap_3 (2727->1) **Misma
...
sky130_fd_sc_hd__decap_4 (2206->201)       |sky130_fd_sc_hd__decap_4 (2206->1) **Misma
...
sky130_fd_sc_hd__decap_8 (2523->203)       |sky130_fd_sc_hd__decap_8 (2523->1) **Misma
...
sky130_fd_sc_hd__tapvpwrvgnd_1 (7407->203) |sky130_fd_sc_hd__tapvpwrvgnd_1 (7407->1) *
...
sky130_fd_sc_hd__fill_2 (2358->116)        |sky130_fd_sc_hd__fill_2 (2358->1) **Mismat
...
sky130_fd_sc_hd__diode_2 (468->76)         |sky130_fd_sc_hd__diode_2 (468->120) **Mism

you can see that cells that should be in parallel the layout are not being reduced. This is likely caused by missing power routing. Can you open the layout and verify that the power grid is connected. The

vsdmemsoc.v

file that you uploaded only has 5 lines. Could you share the full file and your

config.json

file?

Pavan Mantri

06/15/2023, 4:02 PM

I will look into the power grid connection. Here are the files.

config.json vsdmemsoc.v

👍 1

Pavan Mantri

06/16/2023, 5:05 AM

Hi @Mitch Bailey,Here is the pdn.log report. metal straps and rails information is not present.

7-pdn.log

Pavan Mantri

06/16/2023, 5:23 AM

snapshot of layout after floorplan stage

Mitch Bailey

06/16/2023, 6:07 AM

@Pavan Mantri The log file looks good to me. In the layout snapshot, you have

vssd1

vccd1

highlighted, correct? Is the non highlighted power connected the same? Especially worried about the vertical power connection on the right side of the macro. I can take a look at the gds if you want to upload it to your repo.

Mitch Bailey

06/16/2023, 10:35 AM

@Pavan Mantri I looked at the layout and I could see vssd1 and vccd1 power rails next to each other in both horizontally met5 and vertically met4. However, it looks like you’re missing via1-met2-via2-met3-via3 in the routing area. Can you confirm that the routing step completed?

Pavan Mantri

06/16/2023, 11:25 AM

I did run the routing. Attaching the log files.

24-detailed.log 20-global.log

Mitch Bailey

06/16/2023, 2:25 PM

Looks like the routing logs are ok. You could try looking at a design that uses a sram macro to see what config variables were used.

Pavan Mantri

06/17/2023, 5:02 AM

Hi David, I will look into that and then get back to you. Thank you

Open in Slack

Previous Next

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.