Matt Venn
05/31/2023, 9:55 AMinout [MPRJ_IO_PADS-10:0] analog_io
Arman Avetisyan
05/31/2023, 1:19 PMMatt Venn
05/31/2023, 1:53 PMTim Edwards
06/01/2023, 7:38 AMinout
, but that's not really representing an analog signal. It is (sometimes) possible to represent an analog signal with a real-valued input or output, but that's just a hack (a numerical behavioral model of an analog circuit), and it doesn't always work. Shared outputs are the worst problem, because they're illegal for digital signals in verilog. I had a bias circuit, for example, with an array of outputs at different current levels that were supposed to be tied together to add up to the desired total current. But I couldn't make it an "output" pin in verilog because as soon as I tied two of them together, all the verilog parsers immediately flagged it as an error.
So take the casting in the caravel verilog with a bit of skepticism---casting an analog signal in straight-up (digital) verilog is technically incorrect, and only really works as a placeholder for a pin; i.e., if those pins are connected to something analog inside a circuit, then as long as that circuit is a black box, it will work fine for some things like LVS.Matt Venn
06/01/2023, 8:21 AM