is there a reason why the dv simulation in caravel_user_project doesn't respect user_defines.v?

Probably a question for @Marwan Abbas. . .

@Anish Default user_defines.v is pointing to caravel folder, you need modify it to user area. In caravel file: mgmt_core_wrapper/verilog/includes/includes.rtl.caravel Modify : -v $(CARAVEL_PATH)/rtl/user_defines.v To -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v

@Anish Thank you for reporting this issue, we'll fix it ASAP, for now the workaround that @Dinesh A mentioned should work.

thanks!

Precheck would fail if you didn't change the default

user_defines

, but there's no way of knowing if the

user_defines

is correct, as we don't know your intended defines. What you can do is that you can go on the platform and look at the tapeout files, you should be able to identify your default gpio config from the produced caravel netlist, or the gds.

@Marwan Abbas: It is effectively a failure of our tools and methods if we cannot provide a way for the user to simulate the operation of the entire chip with their own

user_defines.v

settings. (@Andrew Wright: Wasn't this a high priority item at some point?)

Tim, Yes. 2 points from rereading the thread. I cannot tell if Dinesh needs to verify his user defines is being developed correctly (your direction on the most recent post above) or verify that a presumably correctly defined user defines is being used in tapeout data as expected. Both steps are obviously required for success.