Hello everyone, I am trying to find a proper sizing methodology (instead of just sweeping and observing results as transient takes a long time) for a 5 stages cross coupled charge pump operating with ultra low power (0.2V) to get good efficiency and output power of 1nW. Is there a method to get the proper sizes? I tried this method in "Eid, Majd & Rodriguez-Villegas, Esther. (2017). Analysis and design of cross-coupled charge pump for low power on chip applications. Microelectronics Journal" and sizing results didn't make any sense. in this publication it was one stage of Charge pump and in its case the input voltage was higher than Vth which is not the same as my case. Is there a way to make these relations work with such number of stages and low voltage ? Thanks

First, make a small design with a open circuit output and see if it works. If it works, use a very large load, such as 1GOhm. Does it still work? Which power do you get this way? If you got 0.1 nW, just multiply everything by 10 and divide your load to 100 MOhm. Test again and see if it is linear.

@Luis Henrique Rodovalho but still how can i come up with the initial sizing for each transistor? I can't just randomize them. can't i ?

This answer is easy: the smallest transistor possible. Your first step is to see if your circuit actually works as it is. Not only that, if your testbench works. Your circuit should work without any load. After that, you resize all your transistors so it can meet your specifications.

gm/id technique is a good methodology for sizing of the transistors. You can follow the book by @Boris Murmann. there are some examples to walk you through the process. One you get the idea of how to use it, you can employ them across several circuits

@ArunAshok I am familiar with gm/id technique. the idea here in charge pump that i am sizing switches so i need to track switching losses and conduction losses and find the optimum sizing at which these losses are minimum. but the problem is the above equations give me results which don't make any sense which i think because they don't apply for subthreshold operation.

If the purpose is switching, then the losses depend only on the width of the nmos(or pmos). But you probably need to size them for the noise performance as well as charge pump creates a lots of noise in the low frequency region