https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
t

Tom

05/22/2023, 5:47 PM
Ngspice raw file output question: Hi all, I'm trying to use the -r flag in ngspice batch mode to specify a raw file to output the simulation results to. The thing is that although ngspice clearly acknowledges the path and file name I specify on the command line because it prints a message to the console detailing it as the binary raw file to output to it doesn't ever actually write a file. Can anyone help? Thanks
a

Amro Tork

05/22/2023, 6:03 PM
Netlist?
@Tom
t

Tom

05/22/2023, 7:37 PM
Thanks @Amro Tork I can get it to you later
s

Stefan Schippers

05/22/2023, 9:11 PM
If the file is not written it is probably because simulation was not started. If using ngspice in batch mode do not use
.control / .endc
constructs, write the simulation commands in the old legacy spice way:
.option savecurrents
.tran ... ...
also look at the .
out
file generated by ngspice in the directory ngspice is running. Warning and error messages go there.
t

Tom

05/22/2023, 9:32 PM
That's interesting @Stephen Schippers but I run in batch mode all the time now using .control and my simulations always run fine but they only write to raw files when I explicitly use the write command from within .control
s

Stefan Schippers

05/22/2023, 9:39 PM
@Tom, you are right, even in batch mode ngspice runs simulation specified in a .control block, however no raw file is produced even if -r xxx.raw is given. If you remove the .control/.endc and write a plain .tran ... (or .dc ... or .ac ...) line then the raw file is generated. I use this command in general:
ngspice -b -r rawfile.raw -o outfile.out  circuit.spice
👍 2
t

Tom

05/22/2023, 9:51 PM
Thank you very much @Stefan Schippers I will try that this evening
👍 1