Hi, I'm trying to run a design through OpenLane as part of an education process. However my Verilog has time delay # in the sequential sections of code. This is not a synthesizable construct but is normally ignored by synthesis tools. Verilator complains about this (as part of the Lint process) and I would like to pass a parameter to Verilator Command line "-no_timing" so this error does not occur. How does one pass parameters to various tools ? I see nothing in the documentation (Verilator for example). What I would like is that every tool can be given parameters which are passed through transparently by the flow tools. If you know how this is possible please let me know. I am using config.json as my parameter set. Thanks.

Verilator lint is newly added feature. For better understanding open a discussion in OpenLane git repo. So developers will respond to it.