#2046 Support VERILOG_INCLUDE_DIRS in linter Pull request opened by piotro888 Adds support for

VERILOG_INCLUDE_DIRS

option to Verilator linter (in

synthesis.tcl

command

run_verilator

) This option is already supported in synthesis by yosys, so it would be nice if it would also work with linter. Without it, some designs that are synthesized fine, cannot pass the linter. If preferred, this option could be renamed to

LINTER_INCLUDE_DIRS

, as a independent option from yosys one. I'm not sure which one would fit better. The-OpenROAD-Project/OpenLane ✅ All checks have passed 30/30 successful checks

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/1e9efe9d0c4f8044d917d022a05ee1706651ed48|1e9efe9d>

- Support

VERILOG_INCLUDE_DIRS

for linting (#2046) The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/RTimothyEdwards/magic/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/magic/commit/5352a235773514492962eb46a6d76d17442151c8|5352a235>

- Updated the SPICE import routine in the toolkit so that it will RTimothyEdwards/magic

Release - 8.3.449 New release published by github-actions[bot] RTimothyEdwards/magic

#2047 PDN pitch error Issue created by kirubakaran-g **While processing the openlane flow of the built-in design namely 'spm', all the forty steps in flow are complete, and the required reports and logs are generated. But, while processing the openlane flow for a simple Half Adder Logic, I got the following error while generating the PDN:** [STEP 6] [INFO]: Generating PDN (log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log [ERROR]: Last 10 lines: [INFO]: Setting input delay to: 2.0 [WARNING STA-0337] port 'wb_clk_i' not found. [INFO]: Setting load to: 0.033442 [INFO]: Setting clock uncertainty to: 0.25 [INFO]: Setting clock transition to: 0.15 [WARNING STA-0559] transition time can not be specified for virtual clocks. [INFO]: Setting timing derate to: 5.0 % [ERROR PDN-0175] Pitch 1.8400 is too small for, must be atleast 6.6000 Error: pdn_cfg.tcl, 92 PDN-0175 child process exited abnormally [ERROR]: Creating issue reproducible... What might be the issue? Thanks in advance. The-OpenROAD-Project/OpenLane

#2049 Update PDK Pull request opened by donn ~

open_pdks

->

e0f692f

Matching efabless/openlane2#275 The-OpenROAD-Project/OpenLane ✅ All checks have passed 30/30 successful checks

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/40e471465d536c6cdca655f9f2518d3941cc1d65|40e47146>

- Update OpenROAD (#2036) The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/c6f02be3b69d2f6cdae21d6ff43cead124195164|c6f02be3>

- Update PDK (#2049) The-OpenROAD-Project/OpenLane

#2050 Request to Bump Yosys (downgrade) to 0.33+6 (git sha1 41b34a193) Issue created by dlmiles Description Please consider revising the recent closed PR #2027 (Bump Yosys) back a few weeks to:

Yosys 0.33+6 (git sha1 41b34a193, clang 10.0.0-4ubuntu1 -fPIC -Os)

Due to flow issues concerning: YosysHQ/yosys#4039 Please feel free to close this issue once you have considered the situation and made a verdict no matter the outcome, I provide this issue to advise of on-going matter. Thanks Expected Behavior yosys-abc Assertion triggered after processing a significant number of designs (estimated worse than 3%) Assertion causes STEP1 to fail due to abort/core-dump like crash, exit status 134 Environment report

Linux OpenLane docker

Reproduction material See linked Yosys issue for test case and log outputs. Relevant log output See linked Yosys issue for test case and log outputs. The-OpenROAD-Project/OpenLane

#280 [macOS-13.4.1] `Segmentation fault: 11` starting `magic` Issue created by gnawhleinad I've installed

magic

following the instructions from `INSTALL_MacOS.md#with-brew`. I've validated that the `configure`1 ran successfully:

Configuration Summary (principle requirements):

X11:          yes
Python3:      yes
OpenGL:       yes
Vector fonts: yes
Cairo:        yes
Tcl/Tk:       yes

I've also validated the

DISPLAY

is set and I'm running

magic

from the XQuartz window:

$ echo $DISPLAY
/private/tmp/com.apple.launchd.2proAh9BYB/org.xquartz:0

Unfortunately,

magic

immediately exits with a `Segmentation fault: 11`: ``` Process: wish8.6 [96060] Path: /opt/homebrew/*/wish Identifier: wish8.6 Version: ??? Code Type: ARM-64 (Native) Parent Process: bash [72771] Responsible: X11.bin [72377] User ID: 501 Date/Time: 2023-11-19 100141.7780 -0800 OS Version: macOS 13.4.1 (22F770820d) Report Version: 12 Anonymous UUID: 82A0E882-AF1C-BA2F-79F6-AB9F63A53DB2 Sleep/Wake UUID: 4A5EA58B-8933-453A-B017-36BA26F99D95 Time Awake Since Boot: 2000000 seconds Time Since Wake: 1860 seconds System Integrity Protection: enabled Crashed Thread: 0 Dispatch queue: com.apple.main-thread Exception Type: EXC_BAD_ACCESS (SIGSEGV) Exception Codes: KERN_INVALID_ADDRESS at 0x0000000000000050 Exception Codes: 0x0000000000000001, 0x0000000000000050 Termination Reason: Namespace SIGNAL, Code 11 Segmentation fault: 11 Terminating Process: exc handler [96060] VM Region Info: 0x50 is not in any region. Bytes before following region: 105553518919600 REGION TYPE START - END [ VSIZE] PRT/MAX SHRMOD REGION DETAIL UNUSED SPACE AT START ---> MALLOC_NANO (reserved) 600018000000-600020000000 [128.0M] rw-/rwx SM=NUL ...(unallocated) Thread 0 Crashed:: Dispatch queue: com.apple.main-thread 0 libX11.6.dylib 0x10e57ee40 XDefaultColormap + 12 1 tclmagic.dylib 0x10d7be140 GrTkInit + 412 2 tclmagic.dylib 0x10d7c0b00 x11SetDisplay + 1004 3 tclmagic.dylib 0x10d7b0000 GrSetDisplay + 620 4 tclmagic.dylib 0x10d8413d8 mainInitAfterArgs + 564 5 tclmagic.dylib 0x10d93dea0 _magic_initialize + 652 6 libtcl8.6.dylib 0x1008bd91c TclInvokeStringCommand + 120 7 libtcl8.6.dylib 0x1008bf068 TclNRRunCallbacks + 80 8 libtcl8.6.dylib 0x10094c5a8 ChildEval + 132 9 libtcl8.6.dylib 0x10094a13c NRInterpCmd + 1692 10 libtcl8.6.dylib 0x1008bf068 TclNRRunCallbacks + 80 11 libtcl8.6.dylib 0x1008bfdcc TclEvalEx + 1640 12 libtcl8.6.dylib 0x100960788 Tcl_FSEvalFileEx + 512 13 libtk8.6.dylib 0x10075f3c8 Tk_MainEx + 1388 14 wish8.6 0x100572e3c main + 56 15 dyld 0x19687bf28 start + 2236 Thread 1: 0 libsystem_pthread.dylib 0x196bced8c start_wqthread + 0 Thread 2: 0 libsystem_pthread.dylib 0x196bced8c start_wqthread + 0 Thread 3:: com.apple.NSEventThread 0 libsystem_kernel.dylib 0x196b93f14 mach_msg2_trap + 8 1 libsystem_kernel.dylib 0x196ba6240 mach_msg2_internal + 80 2 libsystem_kernel.dylib 0x196b9cb78 mach_msg_overwrite + 604 3 libsystem_kernel.dylib 0x196b94290 mach_msg + 24 4 CoreFoundation 0x196cb27e4 __CFRunLoopServiceMachPort + 160 5 CoreFoundation 0x196cb10c4 __CFRunLoopRun + 1208 6 CoreFoundation 0x196cb04b8 CFRunLoopRunSpecific + 612 7 AppKit 0x199ffc334 _NSEventThread + 172 8 libsystem_pthread.dylib 0x196bd3fa8 _pthread_start + 148 9 libsystem_pthread.dylib 0x196bceda0 thread_start + 8 Thread 4: 0 libsystem_kernel.dylib 0x196b9eff0 __select + 8 1 libtcl8.6.dylib 0x1009b71f0 NotifierThreadProc + 628 2 libsystem_pthread.dylib 0x196bd3fa8 _pthread_start + 148 3 libsystem_pthread.dylib 0x196bceda0 thread_start + 8 Thread 5: 0 libsystem_pthread.dylib 0x196bced8c start_wqthread + 0 Thread 0 crashed with ARM Thread State (64-bit): x0: 0x0000000136071a10 x1: 0x0000000000000000 x2: 0x0000000000000000 x3: 0x0000000000000000 x4: 0x0000000000000036 x5: 0x0000000000000035 x6: 0x0000000000000035 x7: 0x000000016f892728 x8: 0x0000000000000000 x9: 0x0000000000000000 x10: 0x0000000000000000 x11: 0x0000000136326910 x12: 0x000000010e2420b8 x13: 0x0000000000000020 x14: 0x0000000000000001 x15: 0x0018000000000001 x16: 0x000000010e57ee34 x17: 0x0000000000000035 x18: 0x0000000000000000 x19: 0x0000000135b14610 x20: 0x0000000000000002 x21: 0x0000000135b5adc0 x22: 0x0000000135ac4090 x23: 0x000000013615b730 x24: 0x0000000000000000 x25: 0x0000000135b5add0 x26: 0x000000013601d290 x27: 0x000000013601d2f0 x28: 0x00000000000014cf fp: 0x000000016f892860 lr: 0x000000010d7be140 sp: 0x000000016f892670 pc: 0x000000010e57ee40 cpsr: 0x20001000 far: 0x0000000000000050 esr: 0x92000006 (Data Abort) byte read Translation fault Binary Images: 0x10056c000 - 0x100573fff wish8.6 (*) <e5231774-8b61-3d29-9f04-04a8688a8592> /opt/homebrew/*/wish8.6 0x100738000 - 0x10083ffff libtk8.6.dylib (*) <887d3269-6be3-3d4d-a7ed-327ef55e3f64> /opt/homebrew/*/libtk8.6.dylib 0x1008ac000 - 0x1009d7fff libtcl8.6.dylib (*) <d0dfb9ec-d5cb-3e77-8fd4-b72df97057be> /opt/homebrew/*/libtcl8.6.dylib 0x10c07c000 - 0x10c087fff libobjc-trampolines.dylib (*) <570c31f7-94c6-3b86-ae44-1694db0a4bcd> /usr/lib/libobjc-trampolines.dylib 0x10d6c4000 - 0x10d96bfff tclmagic.dylib (*) <bec49421-f089-3532-86b7-024723e96597> /usr/local/lib/magic/tcl/tclmagic.dylib 0x10e56c000 - 0x10e65bfff libX11.6.dylib (*) <85a7413a-7238-3ecb-af88-78deb37dc2bf> /opt/X11/*/libX11.6.dylib 0x10d4a0000 - 0x10d4e3fff libGL.1.dylib (*) <15e96a6a-55c1-3a51-a1ec-69340ca81d8d> /opt/X11/*/libGL.1.dylib 0x10d35c000 - 0x10d3bbfff libGLU.1.dylib (*) <b8b8a1bd-dc0d-3df8-b361-51db30a51045> /opt/X11/*/libGLU.1.dylib 0x10d514000 - 0x10d5e3fff libcairo.2.dylib (*) <3f554ab9-d686-307b-b383-ec34ea504ed9> /opt/X11/*/libcairo.2.dylib 0x10d3e8000 - 0x10d41bfff libfontconfig.1.dylib (*) <0ef5df10-dbec-3fa0-a6e9-19dde3252132> /opt/X11/*/libfontconfig.1.dylib 0x10e888000 - 0x10e90bfff libfreetype.6.dylib (*) <083cb0b5-37a3-346d-a77c-96c957aeeab6> /opt/X11/*/libfreetype.6.dylib 0x10d434000 - 0x10d447fff libxcb.1.dylib (*) <335e5b70-9435-366b-a17a-b980bcd5a4f2> /opt/X11/*/libxcb.1.dylib 0x10d62c000 - 0x10d62ffff libXau.6.dylib (*) <aa9a4a03-f4a3-3c9d-8e67-1cbc9682f841> /opt/X11/*/libXau.6.dylib 0x10d640000 - 0x10d677fff libglapi.0.dylib (*) <91fd2107-3155-3182-9a8c-edbb84bdb3f1> /opt/X11/*/libglapi.0.dylib 0x10d464000 - 0x10d46bfff libxcb-glx.0.dylib (*) <dc684108-4977-36bb-9e06-35f12b68912b> /opt/X11/*/libxcb-glx.0.dylib 0x10d488000 - 0x10d48bfff libX11-xcb.1.dylib (*) <1db0a4a4-8bab-3552-9395-145ec5b16d58> /opt/X11/*/libX11-xcb.1.dylib 0x10d6a0000 - 0x10d6abfff libXext.6.dylib (*) <3149eef3-7b2a-3472-b066-5a2a1a14f20e> /opt/X11/*/libXext… RTimothyEdwards/magic

#2051 yosys/synth.tcl: migrate to newer supported drw &amp; drf commands Pull request opened by dlmiles • Add tt05-i2c-bert (https://github.com/dlmiles/tt05-i2c-bert) to CI ~ Replace instances of ABC command

rewrite

with

drw -l

with

SYNTH_ABC_LEGACY_REWRITE

being set to

1

restoring the older functionality (

0

by default) ~ Replace instances of ABC command

refactor

with

drf -l

with

SYNTH_ABC_LEGACY_REFACTOR

being set to

1

restoring the older functionality (

0

by default) ~ Added

delete t:\$print

to

synth.tcl

to fix designs such as PPU with synthesized prints (as in efabless/openlane2#189) Original PR body follows: Re Yosys commands: rewrite & refactor These commands are considered obsolete and unmaintained by Yosys Replacement commands exist in the form of: drw & drf See also: YosysHQ/yosys#4039 #1523 * * * [ci ets] Resolves #2052 Depends on efabless/openlane-ci-designs#3 The-OpenROAD-Project/OpenLane GitHub Actions: Test Design ./designs/ci/y_huff (gf180mcuC/gf180mcu_fd_sc_mcu7t5v0) GitHub Actions: Test Design ./designs/ci/aes_core (sky130A/sky130_fd_sc_hd) GitHub Actions: Test Design ./designs/ci/salsa20 (sky130A/sky130_fd_sc_hd) ✅ 27 other checks have passed 27/30 successful checks

#1523 Synthesis - ABC: + rewrite failure when running yosys-abc Issue created by ramrajrl Description Yosys Synthesis Fails when running ABC, this error happens on a relatively big arithmetic circuit optimization. Please check this thread from YosysHQ for the details of the issue. YosysHQ/yosys#174 (comment) In Openlane setup -- it is this file -->

scripts/yosys/synth.tcl

Expected Behavior

This error happen on a relatively big arithmetic circuit optimization. I have simplified code and post few examples here. They should lead to equivalent synthesis flow. But in some cases ABC fail and in other it is not. Theoretically it could be ABC issue,

I've been in email contact with Alan Mishchenko, the author of ABC, regarding this problem.

This seems to be a known problem with ABC's

rewrite

command with "highly redundant netlists with deep logic". Alan says this is probably not going to be fixed anytime soon because it means a lot of work in obsolete code. He suggests to simply use the newer

drw

command instead of

rewrite

.

I've now added transforming divide and modulo by a constant power of two to simpler operations in commit 11f7b8a. This avoids generating "highly redundant netlists" for the example you gave in the first place.

Please use the newer

drw

command instead of

rewrite

in

scripts/yosys/synth.tcl

Environment report

openlane.log:ERROR: ABC: execution of command ""/build/bin/yosys-abc" -s -f /tmp/yosys-abc-IhLev5/abc.script 2>&1" failed: return code 134.

71.1.1. Executing ABC.
Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-tRZss0/abc.script 2>&1

ABC: + refactor
ABC: An error occurred during computation. The original network is restored.
ABC: + balance
ABC: + rewrite
ABC: yosys-abc: src/base/abc/abcAig.c:167: void abc::Abc_AigFree(abc::Abc_Aig_t*): Assertion `Vec_PtrSize( pMan->vStackReplaceOld ) == 0' failed.
ABC: Flags A, B, or C are not zero.
ERROR: ABC: execution of command ""/build/bin/yosys-abc" -s -f /tmp/yosys-abc-tRZss0/abc.script 2>&1" failed: return code 134.

Reproduction material Please refer to this for the specific testcase, attached makefile and sources (testcase.zip) to reproduce problem. YosysHQ/yosys#174 (comment) Relevant log output

+ fx 
Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
+ mfs 
+ strash 
+ refactor 
An error occurred during computation. The original network is restored.
+ balance 
+ drw 
+ refactor 
+ balance 
+ drw 
+ drw -z 
+ balance 
+ refactor -z 
+ drw -z 
+ balance 
+ retime -D -D 10000 -M 6 
+ scleanup 
Error: The network is combinational.
+ map -p -B 0.2 -A 0.9 -M 0 
The cell areas are multiplied by the factor: <num_fanins> ^ (0.90).
The cell delays are multiplied by the factor: <num_fanins> ^ (0.20).
+ retime -D -D 10000 
+ &get -n 
+ &st 
+ &dch 
+ &nf 
+ &put 
+ buffer -N 25 -S 750.0 
+ upsize -D 10000 
Current delay (5733.16 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
+ dnsize -D 10000                                                                                                                                 
+ stime -p    

With drw instead of rewrite, ABC works fine

The-OpenROAD-Project/OpenLane

#2052 Replace outdated commands in synthesis scripts Issue created by donn Description First reported in #1523 (and mistakenly closed) then resurfaced as #2050: The commands

refactor

and

rewrite

are considered broken by the Yosys team: see this comment from @jix. YosysHQ/yosys#4039 (comment) Proposal

drf

and

drw

are offered as "drop-in" replacements. If

refactor

and

rewrite

are in a state of disrepair, they should be replaced (at the very least for OpenLane 2.) We are, however, weary of unintended side effects. ABC scripts tend to be… incredibly opaque and moody. This will need to be discussed. The-OpenROAD-Project/OpenLane

#2053 PDN pitch error Issue created by kirubakaran-g Description While processing the openlane flow of the built-in design namely 'spm', all the forty steps in flow are complete, and the required reports and logs are generated. But, while processing the openlane flow for a simple Half Adder Logic, I got the following error while generating the PDN: [STEP 6] [INFO]: Generating PDN (log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log [ERROR]: Last 10 lines: [INFO]: Setting input delay to: 2.0 [WARNING STA-0337] port 'wb_clk_i' not found. [INFO]: Setting load to: 0.033442 [INFO]: Setting clock uncertainty to: 0.25 [INFO]: Setting clock transition to: 0.15 [WARNING STA-0559] transition time can not be specified for virtual clocks. [INFO]: Setting timing derate to: 5.0 % [ERROR PDN-0175] Pitch 1.8400 is too small for, must be atleast 6.6000 Error: pdn_cfg.tcl, 92 PDN-0175 child process exited abnormally [ERROR]: Creating issue reproducible... What might be the issue? Thanks in advance. Expected Behavior The flow must be complete. But showing an error in 'PITCH'. Environment report

open_pdks 2a38e86d557197f06d3eefca0fbc161db9e09924
Kernel: Linux v5.15.133.1-microsoft-standard-WSL2
Distribution: ubuntu 22.04
Python: v3.10.12 (OK)
Container Engine: docker v24.0.7 (OK)
OpenLane Git Version: 1e9efe9d0c4f8044d917d022a05ee1706651ed48
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: MISMATCH
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 2a38e86d557197f06d3eefca0fbc161db9e09924, tested: dd7771c384ed36b91a25e9f8b314355fc26561be)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
---
Git Log (Last 3 Commits)

1e9efe9d 2023-11-16T08:28:57+02:00 Support `VERILOG_INCLUDE_DIRS` for linting (#2046) - piotro888 -  (HEAD -> master, tag: 2023.11.17, origin/master, origin/HEAD)
63cb841b 2023-11-14T12:54:37+00:00 Update Verilator (#2045) - Mohamed Gaber -  (tag: 2023.11.15)
64d43462 2023-11-14T07:53:24+02:00 Add tests for most checkers (#2044) - Kareem Farid -  ()
---
Git Remotes

origin  <https://github.com/The-OpenROAD-Project/OpenLane.git> (fetch)
origin  <https://github.com/The-OpenROAD-Project/OpenLane.git> (push)

Reproduction material halfadder_issue.zip Relevant log output

root@LAPTOP-QQMU2CQ2:/openlane# ./flow.tcl -design ha
OpenLane 1e9efe9d0c4f8044d917d022a05ee1706651ed48
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in 'designs/ha/config.json'...
[INFO]: PDK Root: /root/.volare
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /openlane/designs/ha/runs/RUN_2023.11.19_08.15.55
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[WARNING]: PNR_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE
[WARNING]: SIGNOFF_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE
[INFO]: Running linter (Verilator) (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[INFO]: 0 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/3-initial_fp.log)...
[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.
[INFO]: Floorplanned with width 7.36 and height 5.44.
[STEP 4]
[INFO]: Running IO Placement (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/4-io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[STEP 6]
[INFO]: Generating PDN (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/6-pdn.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/6-pdn.log
[ERROR]: Last 10 lines:
[INFO]: Setting input delay to: 2.0
[WARNING STA-0337] port '__VIRTUAL_CLK__' not found.
[INFO]: Setting load to: 0.033442
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[WARNING STA-0559] transition time can not be specified for virtual clocks.
[INFO]: Setting timing derate to: 5.0 %
[ERROR PDN-0175] Pitch 1.8400 is too small for, must be atleast 6.6000
Error: pdn_cfg.tcl, 92 PDN-0175
child process exited abnormally

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
OpenLane TCL Issue Packager

EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD
LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING
THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND.

BY USING THIS SCRIPT, YOU ACKNOWLEDGE THAT YOU FULLY UNDERSTAND THIS DISCLAIMER
AND ALL IT ENTAILS.

Parsing config file(s)…
Setting up /openlane/designs/ha/runs/RUN_2023.11.19_08.15.55/issue_reproducible…
Done.
[INFO]: Reproducible packaged at 'designs/ha/runs/RUN_2023.11.19_08.15.55/issue_reproducible'.
root@LAPTOP-QQMU2CQ2:/openlane# exit

The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/RTimothyEdwards/netgen/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/netgen/commit/a7e859fcde6643d5f45885bcb8c8a3b8445816a8|a7e859fc>

- Corrected an error in parallel_sort and series_sort that does not RTimothyEdwards/netgen

#2054 `Final_Util` metric not extracted properly. Issue created by donn Description Originally reported by @passant5: The value for

Final_Util

metric is

-1

. Expected Behavior The final utilization value should be extracted properly, after detailed routing. Environment report

Kernel: Darwin v23.1.0
Distribution: macOS 14.1
Python: v3.11.5 (OK)
Container Engine: UNKNOWN vUNKNOWN (UNSUPPORTED)
OpenLane Git Version: c6f02be3b69d2f6cdae21d6ff43cead124195164
NOT FOUND: Please install pip using your operating system's package manager.
---
PDK Version Verification Status: FAILED
/Users/donn/efabless/openlane/pdks/sky130A not found.
Traceback (most recent call last):
  File "/Users/donn/efabless/openlane/dependencies/verify_versions.py", line 75, in verify_versions
    raise Exception(f"{pdk_dir} not found.")
Exception: /Users/donn/efabless/openlane/pdks/sky130A not found.

Failed to verify sky130A.
---
Git Log (Last 3 Commits)

c6f02be3 2023-11-19T14:03:46+02:00 Update PDK (#2049) - Mohamed Gaber -  (HEAD -> master, tag: 2023.11.20, origin/master, origin/HEAD)
40e47146 2023-11-19T13:49:04+02:00 Update OpenROAD (#2036) - Mohamed Gaber -  ()
1e9efe9d 2023-11-16T08:28:57+02:00 Support `VERILOG_INCLUDE_DIRS` for linting (#2046) - piotro888 -  (tag: 2023.11.17)
---
Git Remotes

origin  git@github.com:The-OpenROAD-Project/OpenLane (fetch)
origin  git@github.com:The-OpenROAD-Project/OpenLane (push)

Reproduction material N/A Relevant log output

N/A

The-OpenROAD-Project/OpenLane

#2055 Fix extraction of `Final_Util` metric Pull request opened by donn ~ Reimplemented extraction to use a new

metrics.json

that is output by the DRT step. * * * Resolves #2054 The-OpenROAD-Project/OpenLane ✅ All checks have passed 30/30 successful checks

#2056 Issue Survey Fixes Pull request opened by donn ~ Updated install documentation ~ Fixed issue where the issue survey's PDK checker uses

./pdks

instead of

~/.volare

• Dropped

pip

requirement/check: `venv`s include

pip

regardless The-OpenROAD-Project/OpenLane ✅ All checks have passed 30/30 successful checks

#2057 Add a max capacitance variable Issue created by donn Description Other than

CTS_MAX_CAP

(which is expressly for clock-tree synthesis which benefits from a different constraint,) there is no way to set max capacitance with the default SDC file, like you can transition and fanout. Proposal A new PDK variable,

MAX_CAPACITANCE_CONSTRAINT

, to join

MAX_TRANSITION_CONSTRAINT

and

MAX_FANOUT_CONSTRAINT

. The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/d241d1140816739ec9283fafb614d2b0b367663f|d241d114>

- Fix extraction of

Final_Util

metric (#2055) The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/RTimothyEdwards/magic/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/magic/commit/21336607e0ff8db869c6ea0b8a1f2c3eeb97b618|21336607>

- Added checks for GDS scalefactor (DBU) both when reading GDS in RTimothyEdwards/magic

Release - 8.3.450 New release published by github-actions[bot] RTimothyEdwards/magic

#281 DRC Issue created by mi-ye RTimothyEdwards/magic

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/ee452da40ddd9b809f27838c2ffeee3a03510c62|ee452da4>

- Issue Survey Fixes (#2056) The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/f691c8c0712ca6c6645e3fd548985b3cbcf08c78|f691c8c0>

- yosys/synth.tcl: migrate to newer supported drw & drf commands (#2051) The-OpenROAD-Project/OpenLane

#2058 [ERROR]: There are violations in the design after Magic DRC. Issue created by tdtu1002 I'm a newbie and I'm having problems with my design. when running Magic DRC. Magic says I have no DRC errors but there are 56000 violations, what are the violations here? how to fix it ? thanks The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/RTimothyEdwards/magic/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/magic/commit/84af8016081eb5d433a910512a9ff0b6cd319aeb|84af8016>

- Fixed two independent errors, both of which can cause devices to be RTimothyEdwards/magic

Release - 8.3.451 New release published by github-actions[bot] RTimothyEdwards/magic

1 new commit pushed to

<https://github.com/RTimothyEdwards/magic/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/magic/commit/83ed73ac522c6bbd5900240c2d02e399820cbc26|83ed73ac>

- One more change to the "extresist" code which prevents extresist RTimothyEdwards/magic

Release - 8.3.452 New release published by github-actions[bot] RTimothyEdwards/magic