#1825 Maximum transition time set in a weird manner Issue created by donn Description Typically, if the user does not want to explicitly override the maximum transition time set by the PDK, the synthesis script or the SDC file should just fall back to that provided by the lib files. OpenLane, on the other hand, attempts to calculate a heuristic of 0.1*$::env(SYNTH_MAX_TRAN)?? Additionally, $::env(SYNTH_MAX_TRAN) is unused in the

base.sdc

file. Expected Behavior If

SYNTH_MAX_TRAN

is unset, don't set a max transition time. If it is set, use it. Period. Environment report

Kernel: Linux v6.0.19
Distribution: nixos 22.11
Python: v3.10.9 (OK)
Container Engine: docker v20.10.21 (OK)
OpenLane Git Version: a36049b46a768a6fd956330d5c905900736883b6
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

a36049b4 2023-05-28T15:33:09+03:00 [BOT] Update openroad_app (#1801) - Openlane Bot -  (HEAD -> master, tag: 2023.05.29, upstream/master, fix_max_tr)
5880f358 2023-05-24T17:30:26+03:00 Read multi-corner libs while running resizer and CTS (#1804) - Kareem Farid -  (tag: 2023.05.25)
5ee2232d 2023-05-24T17:21:03+03:00 Update Readme to Include Citation (#1820) - Mohamed Gaber -  ()
---
Git Remotes

origin  git@github.com:donn/openlane (fetch)
origin  git@github.com:donn/openlane (push)
upstream        git@github.com:the-openroad-project/openlane (fetch)
upstream        git@github.com:the-openroad-project/openlane (push)

Reproduction material N/A Relevant log output

N/A

The-OpenROAD-Project/OpenLane

#1826 Fix Max Transition Time Usage Pull request opened by donn • Add

SYNTH_MAX_TRAN

to

base.sdc

(if set) ~ Fix syntax error in

all.tcl

• Removed attempt(s) to calculate a default value for

SYNTH_MAX_TRAN

in

all.tcl

,

openroad/cts.tcl

and

yosys/synth.tcl

* * * Resolves #1825 The-OpenROAD-Project/OpenLane ✅ All checks have passed 26/26 successful checks

#1827 yosys synth script inserts buffers after tristates Issue created by mattvenn Description We are using tristates in the design. We noticed while running STA that a buffer followed the tristate. We already have the option turned off in the config to add output buffers:

set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS)

We tracked it down to the yosys synth script calling insbuf:

opt_clean -purge
    insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)

    set stat_libs ""

We are able to work around it with this patch: https://github.com/TinyTapeout/tinytapeout-03p5/blob/main/tt_mux.patch And here's the tt_mux source: https://github.com/TinyTapeout/tt-multiplexer/blob/main/proto/tt_mux.v Expected Behavior openlane shouldn't insert buffers after tristates. Environment report

Kernel: Linux v5.15.0-71-generic
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.21 (OK)
OpenLane Git Version: 4cd0986b3ae550cdf7a6d0fba4e0657012f635d8
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

4cd0986 2023-02-13T14:32:59+02:00 Bugfixes (#1658) - Kareem Farid -  (grafted, HEAD, tag: 2023.02.14)
---
Git Remotes

origin  <https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin  <https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material n/a Relevant log output

n/a

The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by donn

<https://github.com/The-OpenROAD-Project/OpenLane/commit/bee7c9d2401826c88644fd89d942a0119d09ee4b|bee7c9d2>

- Fix Max Transition Time Usage (#1826) The-OpenROAD-Project/OpenLane

#1824 Add `gui.py` Pull request opened by kareefardi + Add

gui.py

. Adding the help message here:

Usage: gui.py [OPTIONS] RUN_DIR

  View specified layout from run_dir using supported viewers

Options:
  --viewer [klayout|openroad]     Viewer option  [default: openroad]
  -f, --format [def|odb|gds]      Layout format to view  [default: odb]
  -s, --stage [cts|floorplan|placement|routing|signoff]
                                  Optionally specify which stage to view
  --help                          Show this message and exit.

+ Mount HOME directory when running

make mount

. + Add

-congestion_report_file

to steps that call global routing The-OpenROAD-Project/OpenLane

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by kareefardi

<https://github.com/The-OpenROAD-Project/OpenLane/commit/6bb1e0dd91227c6bc5ff64309d6a5fb897d4809a|6bb1e0dd>

- Add

gui.py

(#1824) The-OpenROAD-Project/OpenLane

#1829 [BOT] Update openroad_app Pull request opened by openlane-bot This is an automated PR. See the individual commits for details. The-OpenROAD-Project/OpenLane ✅ All checks have passed 26/26 successful checks

#1830 Read top level spef when using STA_MULTICORNER_READ_LIBS Pull request opened by kareefardi The-OpenROAD-Project/OpenLane ✅ All checks have passed 26/26 successful checks

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by kareefardi

<https://github.com/The-OpenROAD-Project/OpenLane/commit/e910d115dc75c51407f652330bce8ed997c45946|e910d115>

- Read top level spef when using STA_MULTICORNER_READ_LIBS (#1830) The-OpenROAD-Project/OpenLane

#1828 Yosys synth check fix Pull request opened by kareefardi Fix doctest Delimt end of warning by final message emitted by yosys in addition to the keyword

warning

* * * Fixes #1822 The-OpenROAD-Project/OpenLane ✅ All checks have passed 26/26 successful checks

#1756 Create script to open layouts in a run in KLayout/OpenROAD Issue created by kareefardi Description

-gui

imports final

odb

view. This can be enhanced to include the major steps:

cts/
floorplan/
placement/
routing/
signoff/
synthesis/

Proposal A script (or scripts) should be provided for both KLayout and OpenROAD so that given a design, a run tag and a major step, it is opened in the GUI. The-OpenROAD-Project/OpenLane

#1831 [ERROR PPL-0021] Horizontal routing tracks not found for layer Issue created by Eyantra698Sumanto Description I am getting the following error:

Horizontal routing tracks not found for layer

while running OpenLane in Caravel at the floorplan stage. Expected Behavior The OpenLane floorplan should run fine. Environment report

Kernel: Linux v5.4.0-80-generic
Distribution: ubuntu 18.04
Python: v3.6.9 (OK)
Container Engine: docker v20.10.12 (OK)
OpenLane Git Version: f9b5781f5ef0bbdf39ab1c2bbd78be8db11b27f2
pip: INSTALLED
pip:venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

f9b5781 2022-07-01T16:04:31+02:00 Fix a bug with `-overwrite` (#1171) - Anton Blanchard -  (HEAD -> master, origin/master, origin/HEAD)
abb9d59 2022-07-01T13:46:02+02:00 Reimplement support for multiple power domains (#1175) - Marwan Abbas -  ()
83b6145 2022-06-26T18:19:11+02:00 Fix #1163 (#1164) - Mohamed Gaber -  ()

Reproduction material 23_06_01_15_08.zip Relevant log output

OpenROAD 0b8b7ae255f8fbbbefa57d443949b84e73eed757 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/sumanto/Desktop/caravel/openlane/dvsdfossbfc/runs/23_06_01_15_08/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/sumanto/Desktop/caravel/openlane/dvsdfossbfc/runs/23_06_01_15_08/tmp/merged.nom.lef at line 905.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /home/sumanto/Desktop/caravel/openlane/dvsdfossbfc/runs/23_06_01_15_08/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/sumanto/Desktop/caravel/openlane/dvsdfossbfc/runs/23_06_01_15_08/tmp/floorplan/3-initial_fp.def
[INFO ODB-0128] Design: dvsdfossbfc
[INFO ODB-0130]     Created 27 pins.
[INFO ODB-0131]     Created 170 components and 1271 component-terminals.
[INFO ODB-0133]     Created 181 nets and 591 connections.
[INFO ODB-0134] Finished DEF file: /home/sumanto/Desktop/caravel/openlane/dvsdfossbfc/runs/23_06_01_15_08/tmp/floorplan/3-initial_fp.def
Found 0 macro blocks.
Using 1u default distance from corners.
[ERROR PPL-0021] Horizontal routing tracks not found for layer 0.
Error: ioplacer.tcl, 60 PPL-0021

The-OpenROAD-Project/OpenLane

#1832 Warn when default `base.sdc` file is used Issue created by donn Description OpenLane uses the included

base.sdc

file transparently if an SDC file is not set. Proposal Designers should generally be using a more... tailored SDC file. Nothing inherently wrong with using

base.sdc

but at the very least, a warning should be printed. The-OpenROAD-Project/OpenLane

#1833 Review OpenLane base SDC file Issue created by passant5 Description Issues identified in the base.sdc: ☐ Clock is not propagated, so, the clock network is ideal. Consider adding

set_propagated_clock [all_clocks]

☐ Derate factor should be multiplied by

100

not

10

in the logging message here Proposal No response The-OpenROAD-Project/OpenLane

#248 Top connection of m5-m4 capacitors extracted as floating Issue created by d-m-bailey Version

8.3.392

There are 7 m4-m5 mimcaps in the design 1 is 6.88x6.89, 3 are 2x2, and 3 are 1x1. The 1x1 capacitors extract with a floating top net.

X11 c2_7893_4697# a_6172_2126# sky130_fd_pr__cap_mim_m3_2 l=1 w=1
X12 c2_531_9153# VSS sky130_fd_pr__cap_mim_m3_2 l=1 w=1
X15 c2_6142_4445# a_6361_537# sky130_fd_pr__cap_mim_m3_2 l=1 w=1

Expect the top connections to be extracted as shown in the layout.

tar xzf lvs.tgz
gunzip RX_Frontend.spice.gz
cd lvs
./run_lvs RX_Frontend ../RX_Frontend.spice ../user_analog_project_wrapper-lvs.gds.gz

Extracted netlist is in

RX_Frontend/ext/RX_Frontend.gds.spice

lvs.tgz user_analog_project_wrapper-lvs.gds.gz RX_Frontend.spice.gz RTimothyEdwards/magic

#1834 [BOT] Update PDK Pull request opened by openlane-bot This is an automated PR. See the individual commits for details. The-OpenROAD-Project/OpenLane GitHub Actions: Regression Test (Test ${{ matrix.test }}) GitHub Actions: Test Design ${{ matrix.design.name }} (${{ matrix.design.pdk }}/${{ matrix.design.scl }}) GitHub Actions: Fetch or Build PDK (gf180mcuC) GitHub Actions: Fetch or Build PDK (sky130A) ✅ 5 other checks have passed 5/9 successful checks

#1835 PDNgen doesn't respect routing halo Issue created by mguthaus Description The power and ground straps are too close to the pins and prevent detailed routing from passing. Expected Behavior It should be able to route the two macros. I tried modifying

FP_PDN_HORIZONTAL_HALO

and

FP_PDN_VERTICAL_HALO

but these don't seem to have any effect. Environment report

Kernel: Linux v6.0.12-76060012-generic
Distribution: pop 20.04
Python: v3.8.10 (OK)
Container Engine: docker v23.0.1 (OK)
OpenLane Git Version: 2ec3bfdd25143ee6b1973d31fdbb612f838594cb
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: MISMATCH
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: e6f9c8876da77220403014b116761b0b2d79aab4, tested: af3485525297d5cbe93c129ea853da2d588fac41)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
---
Git Log (Last 3 Commits)

2ec3bfdd 2023-05-16T21:06:51+03:00 Do not skip STA when `CLOCK_PORT` is not specified (#1797) - Kareem Farid -  (HEAD -> master, tag: 2023.05.17, origin/master, origin/HEAD)
54bfaa3d 2023-05-11T21:01:58+03:00 [BOT] Update openroad_app (#1774) - Openlane Bot -  (tag: 2023.05.12)
587fe72b 2023-05-11T14:51:16+03:00 [BOT] Update PDK (#1712) - Openlane Bot -  ()
---
Git Remotes

origin  <https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin  <https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material Relevant log output

[INFO]: Running Detailed Routing (log: designs/test_sram_macro/runs/foo/logs/routing/24-detailed.log)...
[ERROR]: There are violations in the design after detailed routing.
[ERROR]: Total Number of violations is 12
[ERROR]: Step 24 (routing) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "quit_on_tr_drc" line 7)
    invoked from within
"quit_on_tr_drc"
    (procedure "detailed_routing_tritonroute" line 19)
    invoked from within
"detailed_routing_tritonroute {*}$args"
    (procedure "detailed_routing" line 2)
    invoked from within
"detailed_routing"
    (procedure "run_routing" line 35)
    invoked from within
"run_routing"
    (procedure "run_routing_step" line 7)
    invoked from within
"run_routing_step"} -errorline 1
[

The-OpenROAD-Project/OpenLane

#249 LEF write seems to take forever Issue created by smunaut lef-bug.zip Attached is a test case to reproduce. This was tested with magic 400 and it seems to hang. (I waited 30+ min for this test case but for another attempt I left it to run overnight for 10+ hours) It was working with magic 394 however. RTimothyEdwards/magic

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by kareefardi

<https://github.com/The-OpenROAD-Project/OpenLane/commit/5ba7fa079092a38e48a8248eeca8324256a09db9|5ba7fa07>

- Fix doctest (#1828) The-OpenROAD-Project/OpenLane

#1836 Add --timing to verilator options Pull request opened by mguthaus This allows behavioral SRAM macros to implement hold and setup delays. Otherwise, Verilator would complain and fail that this (or --no-timing) needs to be specified. The-OpenROAD-Project/OpenLane GitHub Actions: Fetch or Build PDK (sky130A) GitHub Actions: Lint Python Code ✅ 4 other checks have passed 4/6 successful checks

#636 OpenSTA hang with tristate Issue created by mattvenn Description This bug was found by @anall. This reduced test case shows the issue: https://github.com/anall/bug-openlane_hang/tree/reduced OpenLane hangs at step 12 trying to print clock skew report. Environment • Operating System Information:

uname -a

Linux matt-desktop 5.11.0-37-generic #41~20.04.2-Ubuntu SMP Fri Sep 24 09:06:38 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux • Docker Version:

docker --version

Docker version 20.10.7, build 20.10.7-0ubuntu1~20.04.2 Reproduction Material • Upload a tarball containing the relevant design - see repo linked above • List the commands used to run the design: • cd $OPENLANE_ROOT; make mount; ./flow.tcl -design bug-openlane_hang Expected behavior The flow to finish. Logs Last lines printed before hanging.

Startpoint: we (input port clocked by clk)
Endpoint: data (output port clocked by clk)
Path Group: clk
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.00    0.00    0.00   clock clk (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          2.00    2.00 ^ input external delay
                  0.02    0.00    2.00 ^ we (in)
     1    0.00                           we (net)
                  0.02    0.00    2.00 ^ input3/A (sky130_fd_sc_hd__buf_1)
                  0.09    0.11    2.11 ^ input3/X (sky130_fd_sc_hd__buf_1)
     1    0.01                           net3 (net)
                  0.09    0.00    2.11 ^ _04_/A (sky130_fd_sc_hd__inv_2)
                  0.02    0.04    2.15 v _04_/Y (sky130_fd_sc_hd__inv_2)
     1    0.00                           _03_ (net)
                  0.02    0.00    2.15 v _09_/TE_B (sky130_fd_sc_hd__ebufn_1)
                  0.10    0.10    2.25 ^ _09_/Z (sky130_fd_sc_hd__ebufn_1)
     1    0.01                           data_c (net)
                  0.10    0.00    2.25 ^ _08_/A (sky130_fd_sc_hd__ebufn_4)
                  0.18    0.23    2.48 ^ _08_/Z (sky130_fd_sc_hd__ebufn_4)
     2    0.02                           data (net)
                  0.18    0.00    2.48 ^ data (inout)
     0    0.02                           data (net)
                                  2.48   data arrival time

                  0.00   10.00   10.00   clock clk (rise edge)
                          0.00   10.00   clock network delay (ideal)
                          0.00   10.00   clock reconvergence pessimism
                         -2.00    8.00   output external delay
                                  8.00   data required time
-----------------------------------------------------------------------------
                                  8.00   data required time
                                 -2.48   data arrival time
-----------------------------------------------------------------------------
                                  5.52   slack (MET)


min_max_report_end
clock_skew_report

The-OpenROAD-Project/OpenLane

#1838 Redundant verilog blackbox options Issue created by mguthaus Description To flag a Verilog module as blackbox, you need two things: 1. specify it in

VERILOG_FILES_BLACKBOX

2. add a comment of

/// sta-blackbox

These seem redundant. Why not either blackbox all the files in the TCL list or look for the comment in all Verilog files? Expected Behavior Use either

VERILOG_FILES_BLACKBOX

or

sta-blackbox

but not both. Environment report

Not relevant

Reproduction material N/A Relevant log output

N/A

The-OpenROAD-Project/OpenLane

#1839 Fix logging message of timing derate Pull request opened by kareefardi Address issue raised in #1833 The-OpenROAD-Project/OpenLane ✅ All checks have passed 26/26 successful checks

#1840 Deprecate `-overwrite` and `-gui` Pull request opened by kareefardi

-gui

is superseded by

gui.py

.

or_gui

should still work for interactive scripts.

-overwrite

has no value since support for resuming the flow is dropped. The-OpenROAD-Project/OpenLane GitHub Actions: Docker Build (amd64) ✅ 5 other checks have passed 5/6 successful checks

1 new commit pushed to

<https://github.com/The-OpenROAD-Project/OpenLane/tree/master|master>

by kareefardi

<https://github.com/The-OpenROAD-Project/OpenLane/commit/85e9dc67fc4c08992fdf6ac2b36acd89807b0a25|85e9dc67>

- [BOT] Update openroad_app (#1829) The-OpenROAD-Project/OpenLane

#1841 some commands are not working for me. Issue created by YashpalRathod14 Description Expected Behavior it should show net connections. Environment report

% python3 ./env.py issue-survey
/usr/bin/python3: can't open file './env.py': [Errno 2] No such file or directory
child process exited abnormally
% exit
bash-4.2$ python3 ./env.py issue-survey
python3: can't open file './env.py': [Errno 2] No such file or directory
bash-4.2$ exit
exit
vsduser@vsdsquadron:~/Desktop/work/tools/openlane_working_dir/openlane$ python3 ./env.py issue-survey
python3: can't open file './env.py': [Errno 2] No such file or directory

Reproduction material na Relevant log output

na

The-OpenROAD-Project/OpenLane

#1842 Error in routing for picorv32a Issue created by mariamrakka Description I am running the design flow example using picorv32a design. I am using commit e910d11 and I have all steps successful up to run_routing, where I am getting the below log of error during detailed routing (note that I am using pdks i have installed separately in open_pdks directory): ``` OpenROAD 9a713f0e8a51769207918da28adfd3c02b854375 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO]: Reading ODB at '/openlane/designs/picorv32a/runs/RUN_2023.06.03_07.02.57/tmp/routing/25-fill.odb'… define_corners Typical read_liberty -corner Typical /home/mariam/OpenLane/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib [WARNING STA-0163] /home/mariam/OpenLane/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib line 23, default_fanout_load is 0.0. [INFO ORD-0030] Using 2 thread(s). [INFO DRT-0149] Reading tech and libs. Units: 1000 Number of layers: 13 Number of macros: 442 Number of vias: 25 Number of viarulegen: 25 [INFO DRT-0150] Reading design. Design: picorv32 Die area: ( 0 0 ) ( 546215 556935 ) Number of track patterns: 12 Number of DEF vias: 0 Number of components: 39492 Number of terminals: 411 Number of snets: 2 Number of nets: 10163 [INFO DRT-0167] List of default vias: Layer mcon default via: L1M1_PR Layer via default via: M1M2_PR Layer via2 default via: M2M3_PR Layer via3 default via: M3M4_PR Layer via4 default via: M4M5_PR [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. Complete 10000 instances. Complete 20000 instances. Complete 30000 instances. [INFO DRT-0164] Number of unique instances = 265. [INFO DRT-0168] Init region query. [INFO DRT-0018] Complete 10000 insts. [INFO DRT-0018] Complete 20000 insts. [INFO DRT-0018] Complete 30000 insts. [INFO DRT-0024] Complete FR_MASTERSLICE. [INFO DRT-0024] Complete Fr_VIA. [INFO DRT-0024] Complete li1. [INFO DRT-0024] Complete mcon. [INFO DRT-0024] Complete met1. [INFO DRT-0024] Complete via. [INFO DRT-0024] Complete met2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete met3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete met4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete met5. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] li1 shape region query size = 453622. [INFO DRT-0033] mcon shape region query size = 456210. [INFO DRT-0033] met1 shape region query size = 112939. [INFO DRT-0033] via shape region query size = 3940. [INFO DRT-0033] met2 shape region query size = 2573. [INFO DRT-0033] via2 shape region query size = 3152. [INFO DRT-0033] met3 shape region query size = 2564. [INFO DRT-0033] via3 shape region query size = 3152. [INFO DRT-0033] met4 shape region query size = 868. [INFO DRT-0033] via4 shape region query size = 64. [INFO DRT-0033] met5 shape region query size = 80. [INFO DRT-0165] Start pin access. [INFO DRT-0076] Complete 100 pins. [INFO DRT-0076] Complete 200 pins. [INFO DRT-0076] Complete 300 pins. [INFO DRT-0076] Complete 400 pins. [INFO DRT-0076] Complete 500 pins. [INFO DRT-0076] Complete 600 pins. [INFO DRT-0076] Complete 700 pins. [INFO DRT-0076] Complete 800 pins. [INFO DRT-0076] Complete 900 pins. [INFO DRT-0077] Complete 1000 pins. [INFO DRT-0078] Complete 1009 pins. [INFO DRT-0079] Complete 100 unique inst patterns. [INFO DRT-0079] Complete 200 unique inst patterns. [WARNING DRT-0087] No valid pattern for unique instance 07761, master is sky130_vsdinv. [WARNING DRT-0087] No valid pattern for unique instance 07777, master is sky130_vsdinv. [INFO DRT-0081] Complete 247 unique inst patterns. [INFO DRT-0082] Complete 1000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 13259 [INFO DRT-0082] Complete 2000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09267 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09269 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09271 [INFO DRT-0082] Complete 3000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09685 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09799 [INFO DRT-0082] Complete 4000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09743 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09690 [INFO DRT-0082] Complete 5000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 09436 [INFO DRT-0082] Complete 6000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08026 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08386 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 10478 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12535 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12502 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12589 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12570 [INFO DRT-0082] Complete 7000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08496 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12636 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08487 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12512 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12664 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 07903 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12663 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08614 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08908 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12721 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08486 [INFO DRT-0082] Complete 8000 groups. @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 12782 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08743 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08516 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08784 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08559 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08590 @@@ dead end inst @@@ dead end inst [ERROR DRT-0085] Valid access pattern combination not found for 08577 @@@ dead end inst @@@ dead end inst [ERR… The-OpenROAD-Project/OpenLane

#1843 [BOT] Update openroad_app Pull request opened by openlane-bot This is an automated PR. See the individual commits for details. The-OpenROAD-Project/OpenLane GitHub Actions: Docker Build (amd64) GitHub Actions: Docker Build (arm64v8) ✅ 4 other checks have passed 4/6 successful checks

1 new commit pushed to

<https://github.com/RTimothyEdwards/magic/tree/master|master>

by RTimothyEdwards

<https://github.com/RTimothyEdwards/magic/commit/6caab5da375f1f3e98e324509c355033c6144a67|6caab5da>

- (1) Corrected an error with extraction in which terminal area and RTimothyEdwards/magic

Release - 8.3.401 New release published by github-actions[bot] RTimothyEdwards/magic