The Logic analyzer pins in mpw2 have been holding me back from testing a lot of parts, so, please help me with my current understanding if you have any idea. I am not able to make LA pins to send data from CPU to user project area. Im not sure what Im missing. I need to send data from processor to User project. Like turn on LA_DATA_OUT (reg_laX_data) 20:24 to 1 but I tried all permutations and combinations with the reg_laX_iena nothing works. My current understanding, reg_laX_oenb -> means nothing if we didnt connect it to anything in your design. reg_laX_iena -> turning on this means giving instructions to the CPU to receive data from that pin. And in the firmware reg_la0_data [31:0] corresponds to la_data_out[31:0] in the caravel/caravan layout frame and so on for other bits. So when we want to configure the LA pins to send data from CPU to user project, one should make the reg_laX_iena for that pin to be 0 and make the reg_laX_data for that pin to be 1?

Looking at the code for the example user project, I see:

// Configure LA[64] LA[65] as outputs from the cpu
        reg_la2_oenb = reg_la2_iena = 0x00000003;

But the user project example may be doing something with the

oenb

signal, and I don't think the setting of

iena

can make any difference for pins used as outputs.

@Praveen raj I'm able to use the logic analyser to enable my designs

Alright, thanks for the comments. I will look into it.

@Praveen raj: What is the letter-number code on your daughterboards? I'd like to take a look at the layout and see if I find anything that looks relevant. Did you have a testbench simulation that exercises control of the user project from the top level through the logic analyzer? Having a working simulation is good for cutting down on the number of possibilities of what could be wrong.

Thanks! SWT Frame location: F4 SLOT: 37 ID: 20025 We do not have a testbench simulation. But I am looking into these aspects. I will update you if I get far with Testbench sim.