Ahmed Reda
04/18/2023, 2:55 AMMitch Bailey
04/18/2023, 3:09 AMcomp.out
file seems to indicate that you have extracted a flattened layout. It is usually much easier to debug a hierarchically extracted LVS result than a flat result. What commands are your using for extraction?Ahmed Reda
04/18/2023, 7:45 AMgds read <cell.gds>
select top cell
flatten <cell_flat>
load <cell_flat>
cellname delete < cell >
cellname rename <cell_flat> < cell >
select top cell
extract do local
extract all
ext2sim labels on
Ext2sim
ext2spice lvs
ext2spice
What commands are used for a hierarchically extraction!Tim Edwards
04/18/2023, 8:16 AMgds read <cell.gds>
exxtract do local
extract all
ext2spice lvs
ext2spice
As Mitch says, you don't want to flatten the cell for LVS, because it will just make it much harder to debug anything that's wrong. You only want to flatten for full R-C extraction because magic's resistance extraction doesn't work well with hiearchy (until one day I get around to fixing it).Ahmed Reda
04/18/2023, 8:25 AMgds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
for the gds
i found this message, how can be fixed!. It affects the extracted file.Tim Edwards
04/18/2023, 8:30 AMAhmed Reda
04/18/2023, 8:44 AMTim Edwards
04/18/2023, 8:51 AMidentify <new_name>
to rename it, and make sure that <new_name>
doesn't contain any brackets.Ahmed Reda
04/18/2023, 9:54 AMMitch Bailey
04/18/2023, 10:57 AMgds flatglob {sk130_fd_pr__*[A-Z]*}
before your gds read
statement?
The size errors on the mosfets in balanced_switch
are actual discrepancies - it’s probably easier to fix the schematic if the simulation results are the same.
The size errors on the resistor in follower_amp
is caused by an extraneous W parameter on the schematic that needs to be removed.
There was an actual connectivity error in dac_3v_8bit
, if your using an older version, it might still be there. There was also a problem with several layout cells exactly overlapping and being extracted twice (or more). The schematic had a similar problem where 2 resistors were placed on top of each other.Ahmed Reda
04/18/2023, 11:12 AMTim Edwards
04/18/2023, 11:16 AMdac_column IS MISSING !!!!
are probably important and indicate something that needs to be resolved in the schematic.Ahmed Reda
04/18/2023, 11:55 AMTim Edwards
04/18/2023, 12:34 PMvdd
that are disconnected in the layout-extracted netlist, although the layout itself looks fine and shows all devices connected correctly on vdd
. I'm investigating.dac_3v_8bit
in place after reading in GDS. So that makes it a clear extraction issue.Ahmed Reda
04/18/2023, 2:35 PMdac_3v_8bit
only can pass LVS. I have checked it as well.
However, it means we can not do the lvs hierarchy for all circuits together. right now.
Should i rely on the simulating the extracted file. right now.Mitch Bailey
04/18/2023, 3:29 PMsky130_fd_pr__res_high_po
is connected to dvss
in the layout while all 361 are connected to vss
in the netlist.Tim Edwards
04/18/2023, 3:49 PMvss
.Ahmed Reda
04/18/2023, 3:51 PMgds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
I suppose it, is a solution for now.
what do you think!Tim Edwards
04/18/2023, 3:53 PMflatten -doinplace dac_3v_8bit
and then extract. Don't save the flattened cell.Ahmed Reda
04/18/2023, 4:01 PMgds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
then i got Circuits match uniquely
I hope, it is an acceptable solutionTim Edwards
04/18/2023, 4:04 PMgds read iamip123m
flatten -doinplace dac_3v_8bit
extract do local
extract all
ext2spice lvs
ext2spice
Ahmed Reda
04/18/2023, 4:08 PM