@Mitch Bailey Excuse me. can you guide me to know how to fix the lvs , please? Note: 1) i usually use an attached simple script to match the generated files from scheme and magic.

Your

comp.out

file seems to indicate that you have extracted a flattened layout. It is usually much easier to debug a hierarchically extracted LVS result than a flat result. What commands are your using for extraction?

I usually used these commands.

gds read <cell.gds>

select top cell

flatten <cell_flat>

load <cell_flat>

cellname delete < cell >

cellname rename <cell_flat> < cell >

select top cell

extract do local

extract all

ext2sim labels on

Ext2sim

ext2spice lvs

ext2spice

What commands are used for a hierarchically extraction!

@Ahmed Reda: If you just want to extract for LVS, you should just be doing:

gds read <cell.gds>
exxtract do local
extract all
ext2spice lvs
ext2spice

As Mitch says, you don't want to flatten the cell for LVS, because it will just make it much harder to debug anything that's wrong. You only want to flatten for full R-C extraction because magic's resistance extraction doesn't work well with hiearchy (until one day I get around to fixing it).

@Tim Edwards @Mitch Bailey when i used

gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice

for the gds i found this message, how can be fixed!. It affects the extracted file.

I have another circuit I was looking at (although it might have been this one?) giving the same error. I am pretty sure it's a bug in magic, and probably comes from handling brackets in the cell name (because it also uses brackets for arrays). There is a quick workaround---either remove any brackets from the cell name, or else replace the array of cells with the same number of individual instances. I will fix the bug when I have a chance to look into it.

I see. which command should be used to remove any brackets from the cell name!.

I think the array name is derived directly from the instance name, so you would select the first instance of the array and type

identify <new_name>

to rename it, and make sure that

<new_name>

doesn't contain any brackets.

@Tim Edwards @Mitch Bailey I made lvs for the hierarchically. should i hack the spice file to match to overcome the bug. As you see.

It may be that your parameterized cells in the layout are not being reduced correctly. Theoretically, it shouldn’t make a difference, but can you try adding

gds flatglob {sk130_fd_pr__*[A-Z]*}

before your

gds read

statement? The size errors on the mosfets in

balanced_switch

are actual discrepancies - it’s probably easier to fix the schematic if the simulation results are the same. The size errors on the resistor in

follower_amp

is caused by an extraneous W parameter on the schematic that needs to be removed. There was an actual connectivity error in

dac_3v_8bit

, if your using an older version, it might still be there. There was also a problem with several layout cells exactly overlapping and being extracted twice (or more). The schematic had a similar problem where 2 resistors were placed on top of each other.

Actually, i confused. When i extract the dac_3v_8bit as a flat, it can pass lvs correctly. However, when extracting dac_3v_8bit hierarchically is not.

@Ahmed Reda: I am also confused by the array "number of subscripts" error, although I think it is ultimately not an error. But it is something I want to look into.

@Tim Edwards @Mitch Bailey,The comparison result is improved as you see . I suppose the extracted level_shifter from layout has an issue.

@Ahmed Reda: The level shifters look fine. There are parts of the power supply net

vdd

that are disconnected in the layout-extracted netlist, although the layout itself looks fine and shows all devices connected correctly on

vdd

. I'm investigating.

@Tim Edwards Yea. That is right. Flattening

dac_3v_8bit

only can pass LVS. I have checked it as well. However, it means we can not do the lvs hierarchy for all circuits together. right now. Should i rely on the simulating the extracted file. right now.

@Ahmed Reda the substrate of 1 of the 361

sky130_fd_pr__res_high_po

is connected to

dvss

in the layout while all 361 are connected to

vss

in the netlist.

Except that that isn't possible. All resistors in the layout are clearly over

vss

.

Thanks @Tim Edwards @Mitch Bailey I would like to share what i did to pass all blocks together. 1-integrate the flatten dac with other IP blocks 2-Extract hierarchy

gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice

I suppose it, is a solution for now. what do you think!

@Ahmed Reda: Just use

flatten -doinplace dac_3v_8bit

and then extract. Don't save the flattened cell.

The first is if i made flatten for gds including (comparator, sample/hold, and dac), then doing lvs. The result indicates an incorrect resistor substrate. The second on is 1-flatten the dac only 2-create a mag file for the a new dac, based on the flatten layout of the dac 3-add the create mag file of the dac as an instance 4-Apply those commands

gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice

then i got Circuits match uniquely I hope, it is an acceptable solution

@Tim Edwards @Mitch Bailey Thanks.👍