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Title
a

Ahmed Reda

04/18/2023, 2:55 AM
@Mitch Bailey Excuse me. can you guide me to know how to fix the lvs , please? Note: 1) i usually use an attached simple script to match the generated files from scheme and magic.
m

Mitch Bailey

04/18/2023, 3:09 AM
Your
comp.out
file seems to indicate that you have extracted a flattened layout. It is usually much easier to debug a hierarchically extracted LVS result than a flat result. What commands are your using for extraction?
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Ahmed Reda

04/18/2023, 7:45 AM
I usually used these commands.
gds read <cell.gds>
select top cell
flatten <cell_flat>
load <cell_flat>
cellname delete < cell >
cellname rename <cell_flat> < cell >
select top cell
extract do local
extract all
ext2sim labels on
Ext2sim
ext2spice lvs
ext2spice
What commands are used for a hierarchically extraction!
t

Tim Edwards

04/18/2023, 8:16 AM
@Ahmed Reda: If you just want to extract for LVS, you should just be doing:
gds read <cell.gds>
exxtract do local
extract all
ext2spice lvs
ext2spice
As Mitch says, you don't want to flatten the cell for LVS, because it will just make it much harder to debug anything that's wrong. You only want to flatten for full R-C extraction because magic's resistance extraction doesn't work well with hiearchy (until one day I get around to fixing it).
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Ahmed Reda

04/18/2023, 8:25 AM
@Tim Edwards @Mitch Bailey when i used
gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
for the gds i found this message, how can be fixed!. It affects the extracted file.
t

Tim Edwards

04/18/2023, 8:30 AM
I have another circuit I was looking at (although it might have been this one?) giving the same error. I am pretty sure it's a bug in magic, and probably comes from handling brackets in the cell name (because it also uses brackets for arrays). There is a quick workaround---either remove any brackets from the cell name, or else replace the array of cells with the same number of individual instances. I will fix the bug when I have a chance to look into it.
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Ahmed Reda

04/18/2023, 8:44 AM
I see. which command should be used to remove any brackets from the cell name!.
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Tim Edwards

04/18/2023, 8:51 AM
I think the array name is derived directly from the instance name, so you would select the first instance of the array and type
identify <new_name>
to rename it, and make sure that
<new_name>
doesn't contain any brackets.
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Ahmed Reda

04/18/2023, 9:54 AM
@Tim Edwards @Mitch Bailey I made lvs for the hierarchically. should i hack the spice file to match to overcome the bug. As you see.
m

Mitch Bailey

04/18/2023, 10:57 AM
It may be that your parameterized cells in the layout are not being reduced correctly. Theoretically, it shouldn’t make a difference, but can you try adding
gds flatglob {sk130_fd_pr__*[A-Z]*}
before your
gds read
statement? The size errors on the mosfets in
balanced_switch
are actual discrepancies - it’s probably easier to fix the schematic if the simulation results are the same. The size errors on the resistor in
follower_amp
is caused by an extraneous W parameter on the schematic that needs to be removed. There was an actual connectivity error in
dac_3v_8bit
, if your using an older version, it might still be there. There was also a problem with several layout cells exactly overlapping and being extracted twice (or more). The schematic had a similar problem where 2 resistors were placed on top of each other.
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Ahmed Reda

04/18/2023, 11:12 AM
Actually, i confused. When i extract the dac_3v_8bit as a flat, it can pass lvs correctly. However, when extracting dac_3v_8bit hierarchically is not.
t

Tim Edwards

04/18/2023, 11:16 AM
@Ahmed Reda: I am also confused by the array "number of subscripts" error, although I think it is ultimately not an error. But it is something I want to look into.
@Ahmed Reda: I would guess that the messages in the netlist output from xschem that say
dac_column IS MISSING !!!!
are probably important and indicate something that needs to be resolved in the schematic.
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Ahmed Reda

04/18/2023, 11:55 AM
@Tim Edwards @Mitch Bailey,The comparison result is improved as you see . I suppose the extracted level_shifter from layout has an issue.
t

Tim Edwards

04/18/2023, 12:34 PM
@Ahmed Reda: The level shifters look fine. There are parts of the power supply net
vdd
that are disconnected in the layout-extracted netlist, although the layout itself looks fine and shows all devices connected correctly on
vdd
. I'm investigating.
@Ahmed Reda, @Mitch Bailey: This one is really bothersome. I reverted magic all the way back to 8.3.306, which is I think before I did the DAC design, and the behavior is the same. I also extracted my original .mag file of the DAC, and that has the same problem. I can make the LVS work correctly (clean except for property errors) by flattening
dac_3v_8bit
in place after reading in GDS. So that makes it a clear extraction issue.
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Ahmed Reda

04/18/2023, 2:35 PM
@Tim Edwards Yea. That is right. Flattening
dac_3v_8bit
only can pass LVS. I have checked it as well. However, it means we can not do the lvs hierarchy for all circuits together. right now. Should i rely on the simulating the extracted file. right now.
@Tim Edwards I made the flatten lvs and i got this result.
m

Mitch Bailey

04/18/2023, 3:29 PM
@Ahmed Reda the substrate of 1 of the 361
sky130_fd_pr__res_high_po
is connected to
dvss
in the layout while all 361 are connected to
vss
in the netlist.
t

Tim Edwards

04/18/2023, 3:49 PM
Except that that isn't possible. All resistors in the layout are clearly over
vss
.
@Ahmed Reda; How did you do the flattening? I got an LVS match after doing it.
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Ahmed Reda

04/18/2023, 3:51 PM
Thanks @Tim Edwards @Mitch Bailey I would like to share what i did to pass all blocks together. 1-integrate the flatten dac with other IP blocks 2-Extract hierarchy
gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
I suppose it, is a solution for now. what do you think!
t

Tim Edwards

04/18/2023, 3:53 PM
@Ahmed Reda: Just use
flatten -doinplace dac_3v_8bit
and then extract. Don't save the flattened cell.
@Ahmed Reda: How was that different from what you did earlier? First you posted a result with an incorrect resistor substrate. Then you posted a result that matches. What happened in between?
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Ahmed Reda

04/18/2023, 4:01 PM
The first is if i made flatten for gds including (comparator, sample/hold, and dac), then doing lvs. The result indicates an incorrect resistor substrate. The second on is 1-flatten the dac only 2-create a mag file for the a new dac, based on the flatten layout of the dac 3-add the create mag file of the dac as an instance 4-Apply those commands
gds read <cell.gds>
extract do local
extract all
ext2spice lvs
ext2spice
then i got Circuits match uniquely I hope, it is an acceptable solution
can you share your commands to pass it directly
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Tim Edwards

04/18/2023, 4:04 PM
gds read iamip123m
flatten -doinplace dac_3v_8bit
extract do local
extract all
ext2spice lvs
ext2spice
1
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Ahmed Reda

04/18/2023, 4:08 PM
@Tim Edwards @Mitch Bailey Thanks.👍