Hi all, I am trying to get familiar with the opensource process flow, so I am running through all the tools with a simple inverter I made. Currently I am stuck on getting LVS to pass. The issue I am running into is a netlist mismatch between my inverter schematic (4 nets) and my inverter layout (6 nets). I imported the spice file of my inverter into Magic, and it placed all the cells and pins, so I just routed everything together. Once I had everything routed I ran the following to extract the layout:

extract all
ext2spice lvs
ext2spice

Once this is done I open netgen and run the following command:

lvs "inv.spice inv" "inv_mag.spice inv_mag" sky130A_setup.tcl

I figure I am doing something wrong when I create my layout, but I am not able to pinpoint what it is. I've attached an image of my layout along with the spice files and the comp.out file. I appreciate any help on this issue. Thanks!

Hey @Joshua Thater, try connecting the NWELL/PWELL guardrings to VCC and VSS respectively. Currently, they’re not connected and don’t get extracted as ports in your primitive mosfet cells.

That seemed to work. Thank you so much!