Dear @Tim Edwards, I made a layout for a transistor matrix (hybrid waffle scheme) for both NMOS and PMOS because I'm doing a multilevel converter, and I've been extracting parasitics for it. Nonetheless, there are some nodes that appear in between the parasitics, which I do not know where they belong. This nodes leave some capacitors floating. In consequence, my simulation doesn't work properly, as I think this causes a kind of short circuit while switching in between states (really high peaks of current in comparison to the non parasitic version). This involves 2 unknown nodes,

dw_2450_2450#

and

dw_2450_15850#

. I thought that labeling both PWELL and DNWELL for NMOS would do the job, but nothing changed. A third node, called

a_400_27200#

, appears for connecting capacitors in between voltage source connections. I suppose it may be the substrate voltage, that sometimes MAGIC generates as VSUBS, but I don't know how to label substrate as it doesn't have a layer to connect to. I've attached the layout, SPICE extracted netlist and the converter schematic with the label names I've used to give some context. The commands that I used for parasitic extraction are the following

extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice

Hope you can help me identify the origin of this 3 unknown labels. Best regards, Vicente Osorio Rivas

Try ext2spice -F, at least for debugging.

@Vicente Osorio: This is a good layout, but you do have floating nodes. This process (sky130) does not have 5- and 6-terminal devices for FETs inside deep nwell structures, so the underlying substrate does not show up as a connection on the device in the schematic or in the netlist. Nevertheless, there are diodes between pwell and deep nwell and between deep nwell and substrate, and these need to be connected to the power supplies to keep them firmly reverse biased. You will need well contacts (nsd / nsc) around the well attached to the deep nwell, and those need to be tied to VP. You will need substrate contacts (psd / psc) around the outside pwell (which is really just p-substrate), and those need to be tied to VN. That will avoid the issue of the floating nodes.