OpenaLane also Supports 180nm, How to do a post-sy...
# openlane
m
OpenaLane also Supports 180nm, How to do a post-synthesis simulation of .v file generated using opensource 180nm pdk , In case of 130nm we need 2 files see the image (sky130_fd_sc_hd.v primitives.v), ... But for 180nm I copied the gf180mcu_fd_sc_mcu7t5v0.v but primitives.v is not available In folder and also got errors ....
a
can you show the rest of simulation log? they seem to be warnings
m
The same error message was for the rest of the simulation. I have not copied the entire message. in the case of 180nm I think, standard cell information is required but the provided file has issues maybe. What is the right way to simulate the netlist (a file received Synthesis), any ideas?
a
the messages seems to be warnings. Ignore if output seems fishy, then this might be the reason
m
No these are errors see the 180nm Image, the counter.out is not generated.
a
i think you are hitting a limitation of icarus verilog
you can either 1. implement the said feature yourself, 2. ask somebody, 3. hack the .v file by foundary, while maintaining the functionality 4. use another simulator
👍 1
m
Sure. I am trying !!
Thanks !1