Is there a way to launch the OpenRoad GUI using op...
# openlane
m
Is there a way to launch the OpenRoad GUI using openlane makefiles so that it includes the STA constraints? (I'm not sure if this is "built in"... I know I could do it through scripting...)
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m
It does load the sdc & liberty data. However I don't see that it loads parasitics so that might be an enhancement
m
@Matt Liberty What is the target for that? I'm just loading the odb file and it doesn't seem to store that info.
Is there a command file somewhere?
m
I see. You can run it from flow.tcl. Thanks.
m
you can run with-gui and it will get automatically invoked
m
Is there a way to do it post-mortem, after a run has finished?
m
That's sort of the use model for it. It started out just for looking at the layout though. It probably needs updating to handle timing post-mortem
m
I hadn't played with it until now (for my upcoming class). It is pretty slick.
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"[ERROR]: CURRENT_ODB is unset." Hrm.
m
You might need to -tag to point at the run you want to load
m
Perfect. i get it. Thanks
Yeah, it looks like something needs to be done to get timing in there. I'll poke at it more.
m
sta.tcl and sta_multi_corner.tcl (depending on your needs) probably have the missing magic
m
Oh, the SDC is loaded, you just need to press "Update" in the GUI to get the results.
m
yes
Anytime you change the timing you should hit update.
m
Same with clock hierarchy. It doesn't seem to show wire delays in the interface though. And the timing is slightly different than the post-GR or rcx timing.
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m
That because no paraasitics have been loaded in the gui.tcl script. You are at best getting wire load models.
If they are loaded you should see the delay in both
m
Ok, I see different results when loading a spef but still no wire delays in the GUI.
It's good enough to give my students an idea. And a reason to encourage them to look at the STA reports. πŸ™‚
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m
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