Hello, I am getting the attached error when I run openlane, can you help me?

[ERROR]: 4 errors found by linter
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_verilator" line 60)
    invoked from within
"run_verilator"
    (procedure "run_verilator_step" line 3)
    invoked from within
"run_verilator_step"} -errorline 1

I am trying to reproduce a project called avsdbgp_3v3_sky130_v2 that is publicly available. In the same environment, when the following was executed in caravel_user_project, "SUCCESS" was obtained without any problem.

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

The environment was just launched today and everything is up to date.

What’s in

user_proj_example/runs/user_proj_example/logs/synthesis/linter.log

?

Thanks for the reply. The following is included.

%Error: Cannot find file containing module: /project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v
%Error: This may be because there's no search path specified with -I<dir>.
        ... Looked in:
             /project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v
             /project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v.v
             /project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v.sv
             obj_dir//project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v
             obj_dir//project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v.v
             obj_dir//project/openlane/user_proj_example/runs/user_proj_example/../../caravel/verilog/rtl/defines.v.sv
%Error: Cannot find file containing module: /project/openlane/user_proj_example/runs/user_proj_example/../../verilog/rtl/user_proj_example.v
%Error: Exiting due to 3 error(s)

The configuration of openlane seems to have changed from 2 years ago.

avsdbgp_3v3_sky130_v2 is 2 years old and has the caravel subdirectory as part of the repo. You might try cloning

caravel_user_project

and replacing the configuration files with the ones from

avsdbgp_3v3_sky130_v2

. The config.tcl should be replaced with config.json.

@Mitch Bailey I cloned

caravel_user_project

and replaced only

verilog/rtl/user_proj_example.v

. The error decreased, but I continue to get the following error.

[INFO]: Running linter (Verilator) (log: user_proj_example/runs/user_proj_example/logs/synthesis/linter.log)...
[ERROR]: 4 errors found by linter
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_verilator" line 60)
    invoked from within
"run_verilator"
    (procedure "run_verilator_step" line 3)
    invoked from within
"run_verilator_step"} -errorline 1

Here is the content of

/home/hayato/test/openlane/user_proj_example/runs/23_08_17_23_02/logs/synthesis/linter.log

%Warning-EOFNEWLINE: /home/hayato/test/openlane/user_proj_example/../../verilog/rtl/defines.v:66:28: Missing newline at end of file (POSIX 3.206).
                                                                                                   : ... Suggest add newline.
   66 | `endif // __GLOBAL_DEFINE_H
      |                            ^
                     ... For warning description see <https://verilator.org/warn/EOFNEWLINE?v=5.009>
                     ... Use "/* verilator lint_off EOFNEWLINE */" and lint_on around source to disable this message.
%Error: /home/hayato/test/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:76:7: syntax error, unexpected real
   76 |   reg real VBGP;
      |       ^~~~
%Error: Exiting due to 1 error(s)

Attached is the

user_proj_example.v

. I have not made any changes from the original avsdbgp_3v3_sky130_v2 repository, but I am getting a syntax error. It may be a problem with the verilog description, but I have tried everything and cannot find a way to deal with the error.

@hayato kimura Ok, it looks like the

avsdbgp_3v3_sky130_v2

module is behavioral verilog that is not intended to be synthesized. Try creating a file with just this module definition in

verilog/rtl/avsdbgp_3v3_sky130v2.v

.

module avsdbgp_3v3_sky130_v2 #(
    parameter BITS = 32
)(

  input EN,
  output VBGP

);

  reg real VBGP;

  initial begin
     if (EN == 1'b1) begin
        VBGP <= 1.19;
     end else begin
        VBGP <= 0.0;
     end
  end

  always @(EN) begin
     if (EN == 1'b1) begin
        VBGP <= 1.19;
     end else begin
        VBGP <= 0.0;
     end
  end

endmodule

Remove the module definition from

verilog/rtl/user_proj_example.v

, and add this file to

VERILOG_FILES

and

VERILOG_FILES_BLACKBOX

in the config.file. Hopefully, this will allow the file to be bypassed by the linter. I believe the linter addition is relatively new, so it might catch things in older projects. I’m not a verilog or linter expert, so this is just a guess. There’s an article here that says that verilog does not permit real values as ports. If it works, please create an issue.

@Mitch Bailey I made the changes as you suggested and got the same error for

avsdbgp_3v3_sky130_v2.v

.

%Error: /home/hayato/avsdbgp_3v3_sky130_v2/openlane/user_proj_example/../../verilog/rtl/avsdbgp_3v3_sky130_v2.v:10:7: syntax error, unexpected real
   10 |   reg real VBGP;
      |       ^~~~

Is there any other way to handle this?

Could you share your

config.json

file?

@Mitch Bailey Attached is the

avsdbgp_3v3_sky130_v2.v

added only to

VERILOG_FILES_BLACKBOX

because adding it to `VERILOG_FILES`would cause the other error attached.

I think the error in the

image.png

file is because the json file is missing a

,

.

@Mitch Bailey We apologize for the simple inadequacy. The other errors are still the same after correcting the ",". The attached file`avsdbgp_3v3_sky130_v2.v` to both

VERILOG_FILES_BLACKBOX

VERILOG_FILES

.

Still looks like a problem with the json file syntax. Trying to figure out what it is…

@Mitch Bailey Sorry, I attached the wrong file. We will send you the correct file. What I have done remains the same below.

attached file`avsdbgp_3v3_sky130_v2.v` to both

VERILOG_FILES_BLACKBOX

VERILOG_FILES

.

Ok. Let’s try making a version for testing and a version for synthesis. Can you copy

avsdbgp_3v3_sky130_v2.v

to

avsdbgp_3v3_sky130_v2.bb.v

and delete

reg real VBGP;

  initial begin
     if (EN == 1'b1) begin
        VBGP <= 1.19;
     end else begin
        VBGP <= 0.0;
     end
  end

  always @(EN) begin
     if (EN == 1'b1) begin
        VBGP <= 1.19;
     end else begin
        VBGP <= 0.0;
     end
  end

then change your

config.json

to use this file?

@Mitch Bailey Understood. I have made the changes and attached the modified file. The error continues to occur.

Sorry for the confusion.

avsdbgp_3v3_sky130_v2.bb.v

should be ONLY

module avsdbgp_3v3_sky130_v2 #(
    parameter BITS = 32
)(

  input EN,
  output VBGP

);

endmodule

@Mitch Bailey My apologies for the misunderstanding. Same error no longer occurs. Another error is occurring as shown in the attachment and is being investigated.

Just guessing about what to do from the error messages shown, but 1. Remove

#( parameter BITS = 32 )

2. Add

/// sta-blackbox

at the top of the

avsdbgp_3v3_sky130_v2.bb.v

file.

@Mitch Bailey Able to continue to avoid the error in step2. Then error in step3 and we are considering it. send 3-initial_fp.log.log and error message.

Try adding these lines to the config file if the files exist

"EXTRA_LEFS": "dir::../../lef/avsdbgp_3v3_sky130_v2.lef",
"EXTRA_GDS_FILES": "dir::../../gds/avsdbgp_3v3_sky130_v2.gds",

@Mitch Bailey As shown in the attached image, no FILE was present. Is it possible that

avsdbgp_3v3_sky130_v2

was GDS generated without using openlane?

try

find -name '*avsbdgp*'

. The file names may be a little different.

I apologize for the trouble I have caused by my misunderstanding. Should I add

avsdbgp_3v3_sky130_v2/Layout

to

caravel/gds/user_analog_project_wrapper_empty.gds

? I will try some more on the subject of this repository.

Looking at the final gds in the repo, shows the attached hierarchy. You can see that there is no

user_proj_example

. It looks like it was created manually as you suggested. You could try to create the gds and lef for

avsdbgp_3v3_sky130_v2

and run openlane with that. Shouldn’t be too hard. 1. Open the

mag/BGR.mag

file in magic 2. Rename the top cell to

avsdbgp_3v3_sky130_v2

3.

lef write -tech -hide 100 -toplayer -pinonly 100

or something to create the lef file in the working directory. 4. move the lef file to the

lef

directory 5.

gds write avsdbgp_3v3_sky130_v2.gds

6. move the gds file to the

gds

directory. 7. You can check the gds with klayout to be sure it’s reasonable.

@Mitch Bailey Thank you for the details. It may take some time, but I will try.

i hope even you install openlane seperately ,now a days we are getting verilator error,thats why i tried commiting to the stabel verion of openlane.. i hope you are usingn an othet tool seems somuch similar openlane synthesis.. if u could try this,,,may it works