@User: The clock will default to (probably) 10MHz from off-chip, as I don't think I can get a single-ended CMOS signal across the pad at any higher frequency than that. If the all-digital PLL works right, then the clock can run at the highest frequency that the STA tools say the Caravel core will run at; Ahmed can tell you what the STA tools currently say about the maximum clock frequency, but it should land around 50MHz or so.

👋 Hello, team! I wanted to ask can we contribute to OPENLANE using GOlang?

#374 Svaricap Update Pull request opened by prabhatdubey92 Fixes #<issue_number_goes_here> • Tests pass • Appropriate changes to README are included in PR IHP-GmbH/IHP-Open-PDK

Hi all! Are the IP blocks offered as part of the open source PDK or do these have to be purchased individually? Where can I get more details on their performance specs? Thanks

@David Muse any idea why it seems as though Omar is getting assigned and in his calendar leads scoring 50 or under when it looks like it should have been in mine? I.e this lead

I've created a design and preformed rtl simulation (which passed successfully) but when preforming gl simulation the clock and most of the signals in user space are unidentified (I think they are all pulled down for some reason)

Hi all, Sorry for the tag @Stefan Schippers but I am making a capacitive DAC for my SAR ADC project. I am using the following figure as a basis, it's working fine with annotate but I want to get the 256 values faster using external viewer using square waves. With the external viewer though I am only getting 0V for my Vout and I can't seem to fix it. Is it related to this simulation warning "Warning: singular matrix: check node Vout"?

Hi all, I am trying to run testbench for LDO with DC analysis and sweeping one voltage to get the VTC but i get some error and not able to proceed? How do i proceed?

Hello, maybe I will have better success on this channel

@Holger Vogt does it make sense to perform

.disto

analysis using IHP Mosfet models or it is not supported ?