Hi, https://github.com/efabless/sky130_sram_macros, for srams in this github, what is the access latency when reading the sram?

Hello Everyone, For the deliverable of the precheck results for a moc design on August 25th, is that the local precheck? Or the efabless website one? Or does it not matter in this case? Thanks a lot!

Does the wishbone bus used in the caravel soc follows the B4 version of the protocol or or is it some other version?

How to rectify 'error during executing openroad script /openlane/scripts/openroad/resizer.tcl' ? any help

I've been getting the following message when hardening user_project_wrapper:

Result: The top level cell failed pin matching.

vccd1 and vssd1 pins are not being connected.

Hi all, My design only uses LA ports to connect to the user space logic. However there’s a statement in efabless website that says:

Checklist for Open-MPW Submission
...
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
...

So do I need to pass every test in the

dv

folder, or is it possible to write my custom test based on the way I use the LA ports? @User @User @User

Can I use gpio pins to transmit analog signals? And what is difference between this io_in and gpio_analog?

I will always set it to none

@User: The clock will default to (probably) 10MHz from off-chip, as I don't think I can get a single-ended CMOS signal across the pad at any higher frequency than that. If the all-digital PLL works right, then the clock can run at the highest frequency that the STA tools say the Caravel core will run at; Ahmed can tell you what the STA tools currently say about the maximum clock frequency, but it should land around 50MHz or so.

👋 Hello, team! I wanted to ask can we contribute to OPENLANE using GOlang?