Hi all! Are the IP blocks offered as part of the open source PDK or do these have to be purchased individually? Where can I get more details on their performance specs? Thanks

@David Muse any idea why it seems as though Omar is getting assigned and in his calendar leads scoring 50 or under when it looks like it should have been in mine? I.e this lead

I've created a design and preformed rtl simulation (which passed successfully) but when preforming gl simulation the clock and most of the signals in user space are unidentified (I think they are all pulled down for some reason)

Hi all, Sorry for the tag @Stefan Schippers but I am making a capacitive DAC for my SAR ADC project. I am using the following figure as a basis, it's working fine with annotate but I want to get the 256 values faster using external viewer using square waves. With the external viewer though I am only getting 0V for my Vout and I can't seem to fix it. Is it related to this simulation warning "Warning: singular matrix: check node Vout"?

Hi all, I am trying to run testbench for LDO with DC analysis and sweeping one voltage to get the VTC but i get some error and not able to proceed? How do i proceed?

Hello, maybe I will have better success on this channel

@Holger Vogt does it make sense to perform

.disto

analysis using IHP Mosfet models or it is not supported ?

@Diarmuid Collins Efabless uses ball bonding

Got my clear on last Friday, I measure xclk at @10MHz and ~@48MHz at IO36. The management SoC seems to work OK, I played with the PLL and measure the changes on xclk successful, but I were unable to test any example that from the CLEAR git, nor any example of the SOFA branch of the synth tools, nor any simple counter (trying to infer clk auto-magically as stated in the Readme). Does anyone have a minimal example that work on the FPGA side? I configure the FPGA with ftdi_fpga.py, does it have a difference if I program the FPGA with process_bit_stream?

Hello everyone, I'm designing a classical opamp. The formula of $(W/L)_3$ requires parameters of maximum voltage threshold of PMOS_3 V_T03 (max) and V_T01 (min). How can I determine these parameters in SKY130a? Thank you for your consideration!