Hello all, I'm trying to correctly run LVS using batch netgen and the SKY130 setup file on a custom-designed cell. The LVS check fails, the number of cells and nets matches and i can't understand the meaning of the error. I'm attaching the netlists, the .mag and the LVS out put, I hope someone here can give me some clues on how to read the comp.out file and solve this issue. I'm using the following command to run netgen: "netgen -batch lvs DFF_v3p1.spice DFF_v3p1_xschem.spice [project_folder]/open_pdks/sky130/sky130A/libs.tech/netgen/sky130A_setup.tcl" p.s.: Since i'm not sure how to run LVS with subck netlists, I commented the magic-generated subcircuit statement manually. I'd really appreciate if anyone could take a look at this!

Hello everyone, I am looking for help to run a gate-level simulation using OpenLane with sky130_fd_sc_hd and QuestaSim. I am having issues with the .sdf file. Basically, I have loaded a design and ran the flow in OpenLane. Now, I am trying to load the following files in QuestaSim:

primitives.v
sky130_fd_sc_hd.v
my_module.v
my_module.sdf

I got these messages when QuestaSim loads the sdf file:

# Loading instances from my_module.sdf
# Loading timing data from my_module.sdf
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(34): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(35): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(44): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(53): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(57): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(58): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(59): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(60): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(68): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(72): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(73): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(74): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(75): Failed to find matching specify timing constraint for SETUP. 
# ** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file "my_module.sdf".
#    Time: 0 ps  Iteration: 0  Instance: /my_module File: my_module.v
# FATAL ERROR while loading design

How can I correctly load the sdf file? Thanks.

Is there a simple way to save ngspice output data in .csv friendly format? wrdata function behaves badly when it mixes positive and negative values to print nice ascii tables.

Hi everyone, I'm trying to create a layout from an xschem schematic, but I'm facing some issues. Here's what I’ve done so far: Created an inverter schematic in xschem and generated the netlist by selecting LVS netlist: Top level is a .subckt from simulation -> LVS window. Imported the devices from the SPICE file (generated by xschem) into Magic and connected them with metal 1. Used these commands to generate the SPICE file from the layout: save file_name.mag extract all ext2sim ext2spice Ran netgen for LVS using: lvs xschem_spice.spice magic_file.spice sky130_setup.tcl However, the netlists are not matching. Can someone guide me where I might be going wrong? Or if you have a tutorial that goes through xschem to Magic and then comparing with LVS, that would be helpful. Thanks in advance!

hey, i'm running into a

[ERROR PSM-0042] Unable to connect macro/pad Instance manchester_baby to the power grid.

error, which i'm struggling to solve i have

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS"

in my

manchester-baby/config.json

and in

lincoln_gfmpw/config.json

(which is basically my version of the user_proj_example) both of the .v source files for those modules are using the ``ifdef USE_POWER_PINS` header, and i can see that they are present in the gate-level versions of the verilog source, but for some reason it just isn't connecting it. interestingly you can see a gap in the openroad gui where it didn't bother. i've attached my issue_reproducible if anyone is able to help, thank you :)

How does openlane calculate power usage?

Hi, I'm planning to design an open-source Standard Cell Library for a specific purpose using the SkyWater 130 PDK. Before starting, I have a couple of questions: 1. Can the SkyWater 130 PDK be interfaced/installed with proprietary toolchains like Cadence and Siemens? Are there supporting files available? 2. Alternatively, I'm considering designing the library entirely with open-source toolchains. Are there reliable open-source tools, preferably tape-out-proven, for end-to-end library design? I've had difficulty finding open-source characterization tools. Your insights or any recommended resources would be highly appreciated. Thanks.

Hello, I have a problem. My simulation in xschem is taking too much time. I ran it for a week, but the simulation didn't even start. I have approximately 10,000 transistors, and I believe that's too many. Do you have any ideas on how to simplify the model I'm using for these transistors ? thanks for your help.

About MAX SLEW, MAX CAPACITANCE and MAX FANOUT violations (warnings) Hi, Our design passes the olane flow with max slew, cap and fanout warnings. I did not change any default config parameter related to slew, cap or fanout. I checked rcx_sta report file: max slew Limit is 1.50 and slew values are 2.19 for all violated pins max fanout Limit is 10, one pin has 36, one pin has 24 and other violations fanout is 16. 36 fanout pin is reset signal, 24 fanout pin is a common IO isolation pin. Other 16 fanout violation pins are internal. max cap Limit is 0.13 and violated pins has 0.19 for all. The design get max slew violation count 350 max fanout violation count 74 max cap violation count 175 We are planning Nov.6 chipignite tapeout. Is it OK to go with these warnings, or should we get rid of them? If we should, how? Regards, Burak

@Stefan Schippers: I was asked today how to export a graph---just the graph---from xschem. I found a roundabout way to do it, but it's a bit of a hack. I found that the graph will load from any raw file that has the same name as the schematic. So I created a new empty schematic named, say, "graph_test", placed just a single graph in it, copied the raw file to "graph_test.raw", loaded the data, configured the graph to what I wanted, and exported it. Did I miss some more direct way to do that? If there isn't a more direct way to do it, could you please add such a method? How about the ability to title the graph? (The ultimate export would be a dump of all the data into a python script that then configures itself to the contents of the graph using matplotlib, but that's probably asking way too much. . .).