Hello all As, I am designing the inverter circuit in xschem and trying to generate the netlist by designing it's symbol as ,I need that spice file to generate the layout in magic.But, when I am generating the netlist ,it's showing this error "undriven node :Vout" due to which the waveform is not generating and it's showing no such vector Vout. So, can anyone please tell me that why this error is coming and how to resolve this error ?

Hello everyone, I am looking for help to run a gate-level simulation using OpenLane with sky130_fd_sc_hd and QuestaSim. I am having issues with the .sdf file. Basically, I have loaded a design and ran the flow in OpenLane. Now, I am trying to load the following files in QuestaSim:

primitives.v
sky130_fd_sc_hd.v
my_module.v
my_module.sdf

I got these messages when QuestaSim loads the sdf file:

# Loading instances from my_module.sdf
# Loading timing data from my_module.sdf
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(34): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(35): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(44): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(53): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(57): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(58): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(59): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(60): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12088) my_module.sdf(68): Failed to find matching specify module path for IOPATH.
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(72): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(73): Failed to find matching specify timing constraint for HOLD. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(74): Failed to find matching specify timing constraint for SETUP. 
# ** Error (suppressible): (vsim-SDF-12090) my_module.sdf(75): Failed to find matching specify timing constraint for SETUP. 
# ** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file "my_module.sdf".
#    Time: 0 ps  Iteration: 0  Instance: /my_module File: my_module.v
# FATAL ERROR while loading design

How can I correctly load the sdf file? Thanks.

How does openlane calculate power usage?

Is there a simple way to save ngspice output data in .csv friendly format? wrdata function behaves badly when it mixes positive and negative values to print nice ascii tables.

Hello all, I'm trying to correctly run LVS using batch netgen and the SKY130 setup file on a custom-designed cell. The LVS check fails, the number of cells and nets matches and i can't understand the meaning of the error. I'm attaching the netlists, the .mag and the LVS out put, I hope someone here can give me some clues on how to read the comp.out file and solve this issue. I'm using the following command to run netgen: "netgen -batch lvs DFF_v3p1.spice DFF_v3p1_xschem.spice [project_folder]/open_pdks/sky130/sky130A/libs.tech/netgen/sky130A_setup.tcl" p.s.: Since i'm not sure how to run LVS with subck netlists, I commented the magic-generated subcircuit statement manually. I'd really appreciate if anyone could take a look at this!

Hi all, I am facing the a routing congestion error in the step "Running Global Routing Resizer Timing Optimizations". This congestion error is independent of the the position of the macros, either if are placed manually our auto. Furthermore this error only pop ups when I used a caravel flow scheme, with really flows there is not any problem. Finally, opening the openroad gui it can be noticed that is due to a "high congestion area" in the center of the design. The strange part of this error is that this step is before placing and routing the inner logic of this design, so it does not make that much sense to talk about congestion when only macros are placed. I would be so glad is somebody could help me out with this problem. The git link of the project is: https://github.com/salb97/efabless_subsystem_caravel and the run is server_config [STEP 14] [INFO]: Running Global Routing Resizer Timing Optimizations (log: designs/efabless_segmentation_memories/runs/server_config/logs/routing/14-resizer_timing.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl [ERROR]: Log: designs/efabless_segmentation_memories/runs/server_config/logs/routing/14-resizer_timing.log [ERROR]: Last 10 lines: [INFO GRT-0101] Running extra iterations to remove overflow. [INFO GRT-0103] Extra Run for hard benchmark. [INFO GRT-0197] Via related to pin nodes: 39480 [INFO GRT-0198] Via related Steiner nodes: 3402 [INFO GRT-0199] Via filling finished. [INFO GRT-0111] Final number of vias: 134804 [INFO GRT-0112] Final usage 3D: 3743051 [ERROR GRT-0118] Routing congestion too high. Check the congestion heatmap in the GUI. Error: resizer_routing_timing.tcl, 39 GRT-0118 child process exited abnormally [ERROR]: Creating issue reproducible...

hey, i'm running into a

[ERROR PSM-0042] Unable to connect macro/pad Instance manchester_baby to the power grid.

error, which i'm struggling to solve i have

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS"

in my

manchester-baby/config.json

and in

lincoln_gfmpw/config.json

(which is basically my version of the user_proj_example) both of the .v source files for those modules are using the ``ifdef USE_POWER_PINS` header, and i can see that they are present in the gate-level versions of the verilog source, but for some reason it just isn't connecting it. interestingly you can see a gap in the openroad gui where it didn't bother. i've attached my issue_reproducible if anyone is able to help, thank you :)

Hi, I'm planning to design an open-source Standard Cell Library for a specific purpose using the SkyWater 130 PDK. Before starting, I have a couple of questions: 1. Can the SkyWater 130 PDK be interfaced/installed with proprietary toolchains like Cadence and Siemens? Are there supporting files available? 2. Alternatively, I'm considering designing the library entirely with open-source toolchains. Are there reliable open-source tools, preferably tape-out-proven, for end-to-end library design? I've had difficulty finding open-source characterization tools. Your insights or any recommended resources would be highly appreciated. Thanks.

About MAX SLEW, MAX CAPACITANCE and MAX FANOUT violations (warnings) Hi, Our design passes the olane flow with max slew, cap and fanout warnings. I did not change any default config parameter related to slew, cap or fanout. I checked rcx_sta report file: max slew Limit is 1.50 and slew values are 2.19 for all violated pins max fanout Limit is 10, one pin has 36, one pin has 24 and other violations fanout is 16. 36 fanout pin is reset signal, 24 fanout pin is a common IO isolation pin. Other 16 fanout violation pins are internal. max cap Limit is 0.13 and violated pins has 0.19 for all. The design get max slew violation count 350 max fanout violation count 74 max cap violation count 175 We are planning Nov.6 chipignite tapeout. Is it OK to go with these warnings, or should we get rid of them? If we should, how? Regards, Burak

Hello, I have a problem. My simulation in xschem is taking too much time. I ran it for a week, but the simulation didn't even start. I have approximately 10,000 transistors, and I believe that's too many. Do you have any ideas on how to simplify the model I'm using for these transistors ? thanks for your help.