About MAX SLEW, MAX CAPACITANCE and MAX FANOUT violations (warnings) Hi, Our design passes the olane flow with max slew, cap and fanout warnings. I did not change any default config parameter related to slew, cap or fanout. I checked rcx_sta report file: max slew Limit is 1.50 and slew values are 2.19 for all violated pins max fanout Limit is 10, one pin has 36, one pin has 24 and other violations fanout is 16. 36 fanout pin is reset signal, 24 fanout pin is a common IO isolation pin. Other 16 fanout violation pins are internal. max cap Limit is 0.13 and violated pins has 0.19 for all. The design get max slew violation count 350 max fanout violation count 74 max cap violation count 175 We are planning Nov.6 chipignite tapeout. Is it OK to go with these warnings, or should we get rid of them? If we should, how? Regards, Burak

@Burak Aykenar There are also these settings

PL_RESIZER_MAX_CAP_MARGIN

to enable this, be sure

PL_RESIZER_DESIGN_OPTIMIZATIONS

is enabled. Other settings you might want to check

PL_RESIZER_BUFFER_INPUT_PORTS
PL_RESIZER_REPAIR_TIE_FANOUT

and their

GLB

equivalents.

"to enable this, be sure

PL_RESIZER_DESIGN_OPTIMIZATIONS

is enabled." good catch :l

Actually, that’s a good question. I don’t know if openroad has the capability to look inside a hard macro to count the number of connections and calculate slew and capacitance.

I got LVS error when enable OPTIMIZATIONS, checked log and mismatches are related to power connections. So, when you enable optimizations, I assume it adds some logic cells, then you can't use SYNTH_ELABORATE_ONLY "1" RUN_FILL_INSERTION "0" RUN_TAP_DECAP_INSERTION "0" But when I use FL and GLB design and timing optimizations, slew violation drops to 1 and cap violations drops to 0. However, fanout violations increased. I will try to do optimizations in macro level first, then disable optimizations in the top level. Hope it works

Did you get fewer warnings?

Well I changed MAX_FANOUT_CONSTRAINT parameter to 8, PL_RESIZER_MAX_SLEW_MARGIN to 10 and GLB_RESIZER_MAX_SLEW_MARGIN to 5 while hardening macros but still get warnings for fanout, but not for slew and cap. Then I run the flow for the wrapper and the number of warnings in the wrapper are exactly the same, even the values for fanout, cap and slew slack. I always try to instantiate macros only and use no std cell in the wrapper (I remember I read this recommendation). So, when I enable PL/GLN_RESIZER_DESIGN/TIMING_OPTIMIZATIONS parameters, I got LVS errors in the wrapper flow and these were releated to power connections. I don't know which config parameters do I have to change in order not to get these LVS errors but if slew, fanout and cap warnings are OK to ignore then I can live with them.

@Burak Aykenar I’m not an expert in this area, so be wary of any suggestions I make. Currently, is this your hierarchy?

user_project_wrapper
  user_proj_example
    hard macros

Designs like this usually only do routing at the top

user_project_wrapper

level, so you might want to run

user_proj_example

with stricter parameters because you won’t be adding buffers at the top level. The other thing you might try, is eliminating the

user_proj_example

level and synthesizing

user_project_wrapper

. This will require some configuration changes to enable standard cell placement at the top level, but may eliminate some of the slew, fanout, and cap warnings. As to whether or not you can ignore the errors, I think it depends on the signal. If it is a relatively stable signal like reset, you might not need to worry too much. clock signals should probably be fixed.

Thanks @Mitch Bailey My hierarchy is user_project_wrapper macro1 macro2 ... macro195 I only have macro instantiations and their pin connections in wrapper file. So no user_proj_example in the design.

So you’ve already flattened your design. If you have one signal that shared between many macros, the only thing I can think of is to do routing with buffer insertion at the top level. You won’t be able to use these at the top level.

SYNTH_ELABORATE_ONLY "1"
RUN_FILL_INSERTION "0"
RUN_TAP_DECAP_INSERTION "0"

I suggest looking at

user_proj_example/config.json

for reference.

Hello, I also got the same error, did you solve the problem. Please give me advice and solutions