@Stefan Schippers, I'm trying to use raw_read -within a launcher symbol tclcommand- to read multiple tran raw files and get them all plotted on a waveform graph, but I can see that raw_read deletes any pre-loaded data. Is there a way to load multiple files and plot them on the same waveform graph, overlaid on top of each other?

Filler generation for Klayout thread @Daniel Schultz @Daniel Arevalos

Hello, Do the recent versions of OpenLane not generate a verilog netlist after

run_cts

stage ?

<!channel> Join us for Chipalooza Workshop: Schematics and Simulation on March 7, 2024, at 10:00 AM. This workshop will cover essential open-source tools for analog and mixed-signal design, including "xschem" for schematic entry and capture, and "ngspice" for simulation. Don't miss this opportunity to enhance your design skills. Register now to secure your spot! https://efabless.zoom.us/webinar/register/WN_0HrgrV41RdCK4lEMdyxybg#/registration

Hello Team, I’m currently working on integrating a closed-source PDK into our OpenLane environment, moving from Skywater-130. I’ve been going over open_pdks [http://opencircuitdesign.com/open_pdks/], but I’m looking for additional resources or guidance specifically tailored for porting closed-source PDKs into OpenLane or OpenROAD. I’m seeking any insights or experiences from similar integration projects. Any shared knowledge or resources would be greatly appreciated. Thanks

#Firesim_ChipYard Hi guys, I have a issue when run "firesim infrasetup" , follow up the guide at https://docs.fires.im/en/stable/Running-OnPrem-Simulations-Tutorial/Running-a-Single-Node-Simulation.html I faced a ERROR "fatal error: experimental/xrt_device.h: No such file or directory" It makes compilation terminate. | _fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build -std=c++17 -include /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/FireSim-generated.const.h -c -o /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/simif_vitis.o /home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc/simif_vitis.cc

2023-05-31 05:44:05,317 [flush       ] [INFO ]  [localhost] out:  [01m [K/home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc/simif_vitis.cc:12:10: [m [K  [01;31m [Kfatal error:  [m [Kexperimental/xrt_device.h: No such file or directory
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out:    12 | #include  [01;31m [K"experimental/xrt_device.h" [m [K
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out:       |           [01;31m [K^~~~~~~~~~~~~~~~~~~~~~~~~~~ [m [K
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out: compilation terminated.
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make[1]: *** [Makefile:45: /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/simif_vitis.o] Error 1
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make[1]: Leaving directory '/home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc'
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make: *** [make/driver.mk:44: /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/FireSim-vitis] Error 2
2023-05-31 05:44:05,321 [flush       ] [INFO ]  [localhost] out: 
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Fatal error: run() received nonzero return code 2 while executing!
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Requested: make DESIGN=FireSim TARGET_CONFIG=FireSimRocketMMIOOnlyConfig PLATFORM_CONFIG=BaseVitisConfig PLATFORM=vitis vitis
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Executed: /bin/bash -l -c "cd /home/tonns/00_Chipyard/01_fire/firesim/deploy/../ && export RISCV=/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools && export PATH=/home/tonns/00_Chipyard/01_fire/firesim/utils/fireperf:/home/tonns/00_Chipyard/01_fire/firesim/utils/fireperf/FlameGraph:/home/tonns/00_Chipyard/01_fire/firesim/sw/firesim-software:/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools/bin:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/bin:/opt/conda/condabin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/home/tonns/00_Chipyard/01_fire/firesim/deploy && export LD_LIBRARY_PATH=/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools/lib && source sourceme-f1-manager.sh --skip-ssh-setup && cd sim/ && make DESIGN=FireSim TARGET_CONFIG=FireSimRocketMMIOOnlyConfig PLATFORM_CONFIG=BaseVitisConfig PLATFORM=vitis vitis"
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Aborting.
2023-05-31 05:44:05,356 [<module>    ] [ERROR]  Fatal error.|

Please refer to the log file to know more information. Do you have any ideas to solve this problem? Best regards, TonNguyen

Hi All, after update/reinstall the open_pdk, and when try to simulate the reram_tb using ngspice I got the following errors: Note: Compatibility modes selected: hs a Error opening osdi lib "/home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi": No such file or directory! Error: Library /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi couldn't be loaded! Circuit: ** sch_path: /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/xschem/sky130_tests/tb_reram.sch Error on line: n.xr1.n1 top 0 xr1.nfilament sky130_fd_pr_reram__reram_model could not find a valid modelname Simulation interrupted due to error! any advice? @Stefan Schippers @Barak Hoffer @mkk @Tim Edwards

Hi there, I cant seem to find the answers to the following questions online (perhaps I don't know what to search for... 1. Once I've launched openlane I cannot access folders outside the environment created by openlane, how do I fix this so I can access files in my project work area without having to copy them into openlane's design folder every time 2. I don't seem to be able to get openlane to use the PDKs that I have installed separately without getting errors from

make mount

3. Once synthesizing a design openlane always breaks-out the designs pins with long wires extended outside the boundary of the hardened block. How do I prevent this from happening and instead just get it to place ports within the design boundary to which I can connect Thanks in anticipation, Tom

Are we not allowed to place fillblock over a glass layer? I get a DRC error saying "can't overlap those layers" when I do this

Upto what frequency i.e. 5 , 10 or 20GHz can RFCMOS designs be done with open source sky130 PDK ? Are SPICE models available in sky130 PDK been characterized using S-parameter data ? As per foundry upto what max. frequency does these models support RF designs ?