Hello, Do the recent versions of OpenLane not generate a verilog netlist after

run_cts

stage ?

It will generate netlist for all the stages

It was not generating, which was why I asked the query

Yes. with latest commit .v files missing for cts stage. @Kareem Farid fyi

The sta reports are also missing in the reports folder. Instead, I can find the all the sta results clubbed together in a single *_sta.log file in the logs folder

you can raise a github issue. So that a team can look into that.

./runs/run10/
├── cmds.log
├── config.tcl
├── logs
│   ├── cts
│   │   ├── 12-cts.errors
│   │   ├── 12-cts.log
│   │   ├── 12-cts.warnings
│   │   ├── 13-cts_sta.errors
│   │   ├── 13-cts_sta.log
│   │   └── 13-cts_sta.warnings
│   ├── floorplan
│   │   ├── 3-initial_fp.errors
│   │   ├── 3-initial_fp.log
│   │   ├── 3-initial_fp.warnings
│   │   ├── 4-io.errors
│   │   ├── 4-io.log
│   │   ├── 4-io.warnings
│   │   ├── 5-tap.errors
│   │   ├── 5-tap.log
│   │   ├── 5-tap.warnings
│   │   ├── 6-pdn.errors
│   │   ├── 6-pdn.log
│   │   └── 6-pdn.warnings
│   ├── placement
│   │   ├── 10-detailed.errors
│   │   ├── 10-detailed.log
│   │   ├── 10-detailed.warnings
│   │   ├── 11-dpl_sta.errors
│   │   ├── 11-dpl_sta.log
│   │   ├── 11-dpl_sta.warnings
│   │   ├── 6-global.errors
│   │   ├── 6-global.log
│   │   ├── 6-global.warnings
│   │   ├── 8-gpl_sta.errors
│   │   ├── 8-gpl_sta.log
│   │   ├── 8-gpl_sta.warnings
│   │   ├── 9-resizer.errors
│   │   ├── 9-resizer.log
│   │   └── 9-resizer.warnings
│   ├── routing
│   ├── signoff
│   └── synthesis
│       ├── 1-synthesis.errors
│       ├── 1-synthesis.log
│       ├── 1-synthesis.warnings
│       ├── 2-sta.errors
│       ├── 2-sta.log
│       └── 2-sta.warnings
├── openlane.log
├── OPENLANE_VERSION
├── PDK_SOURCES
├── reports
│   ├── cts
│   ├── floorplan
│   │   ├── 3-initial_fp_core_area.rpt
│   │   └── 3-initial_fp_die_area.rpt
│   ├── placement
│   ├── routing
│   ├── signoff
│   └── synthesis
│       ├── 1-synthesis.DELAY_0.chk.rpt
│       ├── 1-synthesis.DELAY_0.stat.rpt
│       ├── 1-synthesis_dff.stat
│       ├── 1-synthesis_pre.stat
│       └── 1-synthesis_pre_synth.chk.rpt
├── results
│   ├── cts
│   │   ├── riscv_core.def
│   │   ├── riscv_core.odb
│   │   └── riscv_core.sdc
│   ├── floorplan
│   │   ├── riscv_core.def
│   │   └── riscv_core.odb
│   ├── placement
│   │   ├── riscv_core.def
│   │   ├── riscv_core.nl.v
│   │   ├── riscv_core.odb
│   │   └── riscv_core.pnl.v
│   ├── routing
│   ├── signoff
│   │   ├── riscv_core.lib
│   │   └── riscv_core.sdf
│   └── synthesis
│       ├── riscv_core.sdf
│       └── riscv_core.v
├── runtime.yaml
├── tmp
│   ├── cts
│   │   ├── cts-fastest.lib
│   │   ├── cts-fastest.lib.exclude.list
│   │   ├── cts.lib
│   │   ├── cts.lib.exclude.list
│   │   ├── cts-slowest.lib
│   │   └── cts-slowest.lib.exclude.list
│   ├── dimensions.txt
│   ├── floorplan
│   │   ├── 3-initial_fp.def
│   │   ├── 3-initial_fp.odb
│   │   ├── 3-initial_fp.sdc
│   │   ├── 4-io.def
│   │   ├── 4-io.odb
│   │   ├── 5-tapcell.def
│   │   └── 5-tapcell.odb
│   ├── layers.list
│   ├── merged.max.lef
│   ├── merged.min.lef
│   ├── merged.nom.lef
│   ├── placement
│   │   ├── 7-global.def
│   │   ├── 7-global.nl.v
│   │   ├── 7-global.odb
│   │   ├── 7-global.pnl.v
│   │   ├── 9-resizer.def
│   │   ├── 9-resizer.nl.v
│   │   ├── 9-resizer.odb
│   │   ├── 9-resizer.pnl.v
│   │   └── 9-resizer.sdc
│   ├── routing
│   │   └── config.tracks
│   ├── signoff
│   └── synthesis
│       ├── 1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
│       ├── 1-trimmed.no_pg.lib
│       ├── hierarchy.dot
│       ├── merged.lib
│       ├── post_techmap.dot
│       ├── riscv_core.json
│       ├── synthesis.sdc
│       ├── trimmed.lib
│       └── trimmed.lib.exclude.list
└── warnings.log

Just to update about the

tmp

folder having netlist files --> This is the output after cts stage. It does not contain any verilog netlist files in

tmp/cts

folder

@ArunKumar P.V OpenLane doesn't output a netlist after finishing the CTS stage (not sure why but can be easily changed)

In the eariler versions, it used to do this, which was why I had this expectation

yes

Just to confirm, the following is sufficient to do STA, correct :

read_db /openlane/designs/riscv_core/runs/run1/results/cts/riscv_core.odb

read_liberty /openlane/designs/riscv_core/src/lib/lib_file.lib

link_design riscv_core

read_sdc -echo /openlane/designs/riscv_core/riscv_base.sdc

report_checks -path_delay min_max -fields {nets cap slew input_pins fanout} -digits {4}

the read_verilog command is not needed when we are using the OpenDB, am I correct ?

yes i don't think link_design is needed too

I see Thanks very much @Kareem Farid 🙂