Is it possible to run the OpenROAD gui inside the Openlane docker? When I try to do so I get the following error:

QStandardPaths: XDG_RUNTIME_DIR not set, defaulting to '/tmp/runtime-'
process 9: The last reference on a connection was dropped without closing the connection. This is a bug in an application. See dbus_connection_unref() documentation for details.
Most likely, the application was supposed to call dbus_connection_close(), since this is a private connection.
  D-Bus not built with -rdynamic so unable to print a backtrace
Stack trace:
 0# 0x0000000001035AA6 in openroad
 1# 0x00007F16C53C4400 in /lib64/libc.so.6
 2# gsignal in /lib64/libc.so.6
 3# abort in /lib64/libc.so.6
 4# 0x00007F16BA845655 in /lib64/libdbus-1.so.3
 5# _dbus_warn_check_failed in /lib64/libdbus-1.so.3
 6# 0x00007F16BDAFCBFB in /lib64/libQt5DBus.so.5
 7# QObject::event(QEvent*) in /lib64/libQt5Core.so.5
 8# 0x00007F16C66F5A55 in /lib64/libQt5Core.so.5
 9# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /lib64/libQt5Core.so.5
10# QCoreApplicationPrivate::sendPostedEvents(QObject*, int, QThreadData*) in /lib64/libQt5Core.so.5
11# 0x00007F16C6744A03 in /lib64/libQt5Core.so.5
12# g_main_context_dispatch in /lib64/libglib-2.0.so.0
13# 0x00007F16C235C3F8 in /lib64/libglib-2.0.so.0
14# g_main_context_iteration in /lib64/libglib-2.0.so.0
15# QEventDispatcherGlib::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
16# QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
17# QThread::exec() in /lib64/libQt5Core.so.5
18# 0x00007F16BDAFA3B5 in /lib64/libQt5DBus.so.5
19# 0x00007F16C654BE71 in /lib64/libQt5Core.so.5
20# 0x00007F16C810EEA5 in /lib64/libpthread.so.0
21# clone in /lib64/libc.so.6
QThread::wait: Thread tried to wait on itself
QMutex: destroying locked mutex
QThread: Destroyed while thread is still running
Stack trace:
 0# 0x0000000001035AA6 in openroad
 1# 0x00007F16C53C4400 in /lib64/libc.so.6
 2# gsignal in /lib64/libc.so.6
 3# abort in /lib64/libc.so.6
 4# 0x00007F16C6538CE1 in /lib64/libQt5Core.so.5
 5# QThread::~QThread() in /lib64/libQt5Core.so.5
 6# 0x00007F16BDAFA5D9 in /lib64/libQt5DBus.so.5
 7# 0x00007F16C53C7CE9 in /lib64/libc.so.6
 8# 0x00007F16C53C7D37 in /lib64/libc.so.6
 9# 0x0000000001035ACB in openroad
10# 0x00007F16C53C4400 in /lib64/libc.so.6
11# gsignal in /lib64/libc.so.6
12# abort in /lib64/libc.so.6
13# 0x00007F16BA845655 in /lib64/libdbus-1.so.3
14# _dbus_warn_check_failed in /lib64/libdbus-1.so.3
15# 0x00007F16BDAFCBFB in /lib64/libQt5DBus.so.5
16# QObject::event(QEvent*) in /lib64/libQt5Core.so.5
17# 0x00007F16C66F5A55 in /lib64/libQt5Core.so.5
18# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /lib64/libQt5Core.so.5
19# QCoreApplicationPrivate::sendPostedEvents(QObject*, int, QThreadData*) in /lib64/libQt5Core.so.5
20# 0x00007F16C6744A03 in /lib64/libQt5Core.so.5
21# g_main_context_dispatch in /lib64/libglib-2.0.so.0
22# 0x00007F16C235C3F8 in /lib64/libglib-2.0.so.0
23# g_main_context_iteration in /lib64/libglib-2.0.so.0
24# QEventDispatcherGlib::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
25# QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
26# QThread::exec() in /lib64/libQt5Core.so.5
27# 0x00007F16BDAFA3B5 in /lib64/libQt5DBus.so.5
28# 0x00007F16C654BE71 in /lib64/libQt5Core.so.5
29# 0x00007F16C810EEA5 in /lib64/libpthread.so.0
30# clone in /lib64/libc.so.6

Does anyone have experience with the rotation of (SRAM) macros? I have a SRAM macro I want to rotate, and the way I do it is by setting the macro.cfg to S instead of N.

rvj1_soc          1162  1552 N
iram_inst         1100  800  S
dram_inst         1100  2400 N
uart_inst         500   1500 N

But when I do this I get the following error:

[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: user_project_wrapper/runs/user_project_wrapper/logs/routing/15-detailed.log
[ERROR]: Last 10 lines:
[INFO DRT-0028]   Complete met5.
[INFO DRT-1000] Pin iram_inst/din0[27] not in any guide. Attempting to patch guides to cover (at least part of) the pin.
[WARNING DRT-1001] No guide in the pin neighborhood
[WARNING DRT-0215] Pin iram_inst/din0[27] not covered by guide.
[WARNING DRT-0215] Pin iram_inst/din0[27] not covered by guide.
[WARNING DRT-0225] iram_din0\[27\] 2 pin not visited, fall back to feedthrough mode.
[WARNING DRT-0224] iram_din0\[27\] 2 pin not visited, number of guides = 8.
[ERROR DRT-0218] Guide is not connected to design.
Error: droute.tcl, 46 DRT-0218

What is the problem here?

So I'm not a klayout user at all, so I'm hoping this is a simply mistake, but when opening

user_project_wrapper.gds

from the

results/klayout

directory, I see the

user_project_wrapper

that includes several lower-level macros. Fine. But I also see the lower-level macros opened separately in the same window. All of these pieces are somewhat on top of one-another and proportioned different... like the lower-level macros are using a different database unit value compared to

user_project_wrapper.gds

. Am I doing something obviously incorrect? Thanks.

@User these are the correct syntaxes for resistors:

XR1 M net1 B sky130_fd_pr__res_iso_pw W=2.65 L=2.65 mult=1 m=1
XR2 M net2 B sky130_fd_pr__res_generic_nd W=1 L=1 mult=1 m=1
XR3 M net3 B sky130_fd_pr__res_generic_pd W=1 L=1 mult=1 m=1
XR5 M net5 B sky130_fd_pr__res_high_po W=1 L=1 mult=1 m=1
XR6 M net6 B sky130_fd_pr__res_high_po_0p35 W=0.35 L=1 mult=1 m=1
XR7 M net7 B sky130_fd_pr__res_high_po_0p69 W=0.69 L=0.69 mult=1 m=1
XR8 M net8 B sky130_fd_pr__res_high_po_1p41 W=1.41 L=1.41 mult=1 m=1
XR9 M net9 B sky130_fd_pr__res_xhigh_po W=1 L=1 mult=1 m=1
XR10 M net10 B sky130_fd_pr__res_xhigh_po_0p35 W=0.35 L=0.35 mult=1 m=1
XR11 M net11 B sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=0.69 mult=1 m=1
XR12 M net12 B sky130_fd_pr__res_xhigh_po_1p41 W=1.41 L=1.41 mult=1 m=1

Resistors with _0pnn or_1pnn suffixes can be used only with specified width. For capacitors here is a sample for vertical metal capacitors:

XC2 G 0 0 0 sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5 W=1 L=1 mult=1 m=1

and these are mim (Metal-Insulator-Metal) capacitors:

XC6 c0 c1 sky130_fd_pr__cap_mim_m3_1 W=1 L=1 MF=1
XC7 c0 c1 sky130_fd_pr__cap_mim_m3_2 W=1 L=1 MF=1

Values for resistances must be calculated from process parameters: Rho for resistors and capacitance per unit area for caps. As an experimental feature xschem on some resistors is displaying the nominal value (keep in mind that silicon resistors are not perfectly constant, they vary with biasing conditions and temperature). If people like that i can add this for capacitors and remaining resistors.

Good day, I am trying to create a layout for my CMOS inverter design using Magic and so I generated the netlist after completing the schematics and checking that the simulations were accurate, and yeah, i imported the spice netlist into magic so as to create my layout from there instead of starting from scratch. And so the picture below shows metal1 with the magenta (very light purple) colour and then a part of my PMOS transistor showing below, basically, i want to connect the metal1 to both the bulk and the source of the PMOS transistor, but looking at the colours before me, I got a little confused, my source is showing the colour labelled as viali and I'm not too sure what the bulk colour represents in my own layout, but my concern is the source that's looking like viali, I was expecting something different. So basically, I need help in connecting the metal contact to the source and bulk of my PMOS transistor.

Hey everyone. I am having some issues with LVS in precheck phase. we have a macro in our design in which SRAM macro from skywater is used. hence its a submacro in the top wrapper. LVS passed inside the flow but in prechecks it failed cause of some mismatches with this sram macro.

In my top.sch the symbols are missing. I just updated open-pdk.

Is there a Seth at efabless ? I just got a voicemail but whoever it was started speaking too early and beginning of message was cut so all I got was a reference to an email I never got and the name "Seth" 😅

Question: Is the Sky130 suitable for a BiCMOS process?

Hi all, I am about to install the gf180 pdk and am wondering what sigma process is it? 3 I presume. Also, are they 1k/sq poly resistors available in the open source pdk? I hear there are 3 variants - A, B and C. Are all those available? If so, what do people generally reccomend and does the choice of A, B or C impact how I download / install the pdk? Thanks