@Tim Edwards Hi We have the commercial SKY130 PDK in Cadence virtuoso . It has all the libraries the open source does except the RRAM. So I would like to ask if there is a way to include the RRAM library available in the open source PDK in Cadence. I know how to include the verilog-a model, but I am curious about its Layout files with DRC and LVS files. Also, the commercial PDK has only one pdk, it’s not divided into two sub pdks like the open source one SKY130A and SKY130B, any idea? Thanks

Hello everyone. How can I simulate Noise figure and OIp3 with NgSpice?

@User these are the correct syntaxes for resistors:

XR1 M net1 B sky130_fd_pr__res_iso_pw W=2.65 L=2.65 mult=1 m=1
XR2 M net2 B sky130_fd_pr__res_generic_nd W=1 L=1 mult=1 m=1
XR3 M net3 B sky130_fd_pr__res_generic_pd W=1 L=1 mult=1 m=1
XR5 M net5 B sky130_fd_pr__res_high_po W=1 L=1 mult=1 m=1
XR6 M net6 B sky130_fd_pr__res_high_po_0p35 W=0.35 L=1 mult=1 m=1
XR7 M net7 B sky130_fd_pr__res_high_po_0p69 W=0.69 L=0.69 mult=1 m=1
XR8 M net8 B sky130_fd_pr__res_high_po_1p41 W=1.41 L=1.41 mult=1 m=1
XR9 M net9 B sky130_fd_pr__res_xhigh_po W=1 L=1 mult=1 m=1
XR10 M net10 B sky130_fd_pr__res_xhigh_po_0p35 W=0.35 L=0.35 mult=1 m=1
XR11 M net11 B sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=0.69 mult=1 m=1
XR12 M net12 B sky130_fd_pr__res_xhigh_po_1p41 W=1.41 L=1.41 mult=1 m=1

Resistors with _0pnn or_1pnn suffixes can be used only with specified width. For capacitors here is a sample for vertical metal capacitors:

XC2 G 0 0 0 sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5 W=1 L=1 mult=1 m=1

and these are mim (Metal-Insulator-Metal) capacitors:

XC6 c0 c1 sky130_fd_pr__cap_mim_m3_1 W=1 L=1 MF=1
XC7 c0 c1 sky130_fd_pr__cap_mim_m3_2 W=1 L=1 MF=1

Values for resistances must be calculated from process parameters: Rho for resistors and capacitance per unit area for caps. As an experimental feature xschem on some resistors is displaying the nominal value (keep in mind that silicon resistors are not perfectly constant, they vary with biasing conditions and temperature). If people like that i can add this for capacitors and remaining resistors.

Hello, this is an issue related to #C0750383B2M I am having trouble with parametric noise runs. The core problem is this bit of code:

alter vvgs_ctrl 0.8
  op
  print Vp1p8hvt#branch
  noise v(src_n1p8lvt) Vvgs_ctrl dec 1000 100 10e9
  print onoise_total
  ; reset
  alter vvgs_ctrl 1.2
  op
  print Vp1p8hvt#branch
  noise v(src_n1p8lvt) Vvgs_ctrl dec 1000 100 10e9
  print onoise_total

This is the core of my loop, I alter a parameter and then re-run the simulation. I have included the

op

command just to verify the

alter

command is doing something. This is what it returns:

Using SPARSE 1.3 as Direct Linear Solver
 Reference value :  0.00000e+00
No. of Data Rows : 1
vp1p8hvt#branch = 5.9080065507013344e-07
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

No. of Data Rows : 8001

No. of Data Rows : 1
onoise_total = 1.2877645416968548e-05
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

No. of Data Rows : 1
vp1p8hvt#branch = 2.3014385629361719e-05
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

No. of Data Rows : 8001

No. of Data Rows : 1
onoise_total = 1.2879064884219959e-05

The branch current increases, however the output noise seems to return the original value. When I simulate at

vctrl=1.2

directly, I get the (expected) noise increase. I saw this: https://sourceforge.net/p/ngspice/discussion/133842/thread/fcd70adf/ So I tried adding the

reset

command, but it kills the sim:

Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

No. of Data Rows : 1
vp1p8hvt#branch = 2.3014385629361719e-05
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver
Error: no data saved for Noise analysis; analysis not run
doAnalyses: not found

noise simulation(s) aborted
Warning from checkvalid: vector onoise_total is not available or has zero length.

Any ideas? Thank you.

Hello, I am following the "Open Source Analog Design Flow" document to build Xyce which depends on Trilinos. I follow the instructions to build a parallel version of Trilinos which builds fine but when I attempt to configure Xyce it complains with:

checking for Teuchos_SerialDenseMatrix.hpp... no
configure: error: Unable to compile a test program against Trilinos that includes Teuchos_Serial_DenseMatrix.hpp.  It is possible Trilinos was not properly configured or the environment has changed since Trilinos was installed.  See config.log for more information.

I seem to recall that when I last built Xyce I had to resort to a serial build (the clue is in the name of the missing file) unless that's a false memory. Any ideas on what might be wrong given I follow the recipe precisely?

I want to run DRC on GDS in klayout for sky130 pdk. Any help on how this can be done? There are several ways mentioned on slack but its still not clear.

xschem can't load the raw sim data on startup as its path is wrong. After running simulation, the path is fixed and it can load it

How does one go about finding the Avth (threshold mismatch) of the devices in this PDK? I am currently trying to calculate threshold voltage mismatch (Av / WL) for a simple flash ADC design that uses strongARM comparators.

Hello! I am completely new to OpenRAM. Currently I am running a compilation + characterization run. The compilation script seems to be taking quite a long time to run. But I noticed only 1 CPU core being utilized. • Is this the default setting and is there a way to configure multiple cores to be used to speed up the process ? (Or, is the nature of the various steps inherently single threaded ?) • Also, is there a method to pause and resume the execution at a later point of time ? EDIT: Already tried adding num_threads=3 in the config file and observed no change.

Is it possible to import spice netlist generated from xschem in Klayout for schematic driven layout (SDL) ? Something similar to as done in magic.