When I paired my project (neuron_core_32, I successfully ran openlane with wishbone bus interfaces) into user_project_wrapper (check for me to see if I did it correctly). When running, it gives the error: [ERROR GRT-0039] Found pin clk outside die area in instance mprj.

Is your macro placed correctly? Does it fit within the die area? Your

RT_MAX_LAYER

is set at

met4

. You probably want to change that to

met5

for the top

user_project_wrapper

cell. Make sure you have this file

dir::fixed_dont_change/user_project_wrapper.def

Mitch Baile How do I determine my macros? Die are of the user_proj_example : "DIE_AREA": "0 0 2300 2500",

Macro placement is usually in

macro.cfg

Is it the area of ​​my user_proj_example block?

openlane/user_project_wrapper/macro.cfg

. It should be the location of

neuron_core_32

.

How can I know its exact location? Do you mean "DIE_AREA": "0 0 2300 2500"?

Can you open

openlane/user_project_wrapper/macro.cfg

? The

DIE_AREA

is the total area.

I checked again, I didn't use the mphr macro, but when I edited it and ran it again, it still had an error at step 31, hold time violation. Can you guide me on how to configure the parameters in config.tcl for optimization? Can it be designed?

Sorry, I don’t have much experience there. Maybe repost in the channel? With the top level

SYNTH_ELABORATE_ONLY

, there’s not much the resizer can do to fix cap, slew, setup/hold, and fanout errors. Some people flatten the user_proj_example and synthesize the top level to overcome the problem.

sure. This is my macro file. I'm setting up by die area because I don't know how to define it. I think I need to relocate the macro because I have errors caused by the floorplanning, placement and routing process

Looking for advice on how to get rid of hold errors. Can someone from the channel comment on this thread?