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Hello! I am completely new to OpenRAM. Currently I am running a compilation + characterization run....
# openram
a
Hello! I am completely new to OpenRAM. Currently I am running a compilation + characterization run. The compilation script seems to be taking quite a long time to run. But I noticed only 1 CPU core being utilized. • Is this the default setting and is there a way to configure multiple cores to be used to speed up the process ? (Or, is the nature of the various steps inherently single threaded ?) • Also, is there a method to pause and resume the execution at a later point of time ? EDIT: Already tried adding num_threads=3 in the config file and observed no change.
m
Which simulator are you using? Are you characterizing too? That can be quite slow (days!)
There is no way to pause, but you can compile (sram_compile.py) and then later simulate (sram_char.py)
a
Hi, Yes, I am running characterization too. But it has not reached till that point yet. From the log print, the simulator used is Xyce
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Performing simulation-based characterization with Xyce
Other tools: drc, pex -> magic (8.3.462) lvs -> netgen (1.5.271) ---------- Actually, it has ended now, but LVS has failed. The run is for a single-port SRAM using sky130 and it looks like, there are already two issues raised on GitHub for similar LVS mismatches. https://github.com/VLSIDA/OpenRAM/issues/217 https://github.com/VLSIDA/OpenRAM/issues/220
I tried a few examples given in the 
macros/sram_configs
folder It seems like the issue is specific to SP RAM as DP RAM compilation for sky130 has no issues based on the examples that I tried 
sky130_sram_1rw_tiny.py ==> Fails
sky130_sram_1rw1r_tiny.py ==> Completed without errors
m
Yes, we've had periodic issues that depend on the version of magic and netgen. It will take a while to debug it. It is likely not really a mismatch though.
a
I see. Thanks very much for this particular info, @Matthew Guthaus I will search in the github issues first to see if anyone has documented a working version combination.
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