Hi everyone.
According to the file caravel_user_project_analog/xschem/analog_wrapper_tb.spice. I can...
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Shuo Lai
07/04/2021, 9:27 PMHi everyone.
According to the file caravel_user_project_analog/xschem/analog_wrapper_tb.spice. I can do simulation with the wrapper. Is there any method to run the simulation with pad?
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Tim Edwards
07/05/2021, 3:50 PMThe main problem is lack of symbols for xschem. In principle, you would just make a symbol to represent the pad and then have the testbench include the SPICE library for sky130_ef_io.spice. If you simulate the analog connections to the GPIO cells, then you would want to make sure that the inp_dis and oeb lines are set high to turn off the digital parts; there's no particular need to simulate the digital control block in front of the pad.
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Shuo Lai
07/05/2021, 6:06 PMThank you for your reply. I still have some questions. I would like to use ngspice and spice netlist instead of xschem to do the simulation.
1. Which IO on pad should I use for VREG (output of the LDO)?
2. https://github.com/efabless/caravel/blob/develop/spi/lvs/chip_io_alt.spice Can I use this file as the spice model for the caravan pad? (It seems that it is the caravel pad and not sure if there is another file for the caravan pad.)
3. Is there any analog pads? If there are, are all the analog pads added in caravan using bare pads? Or maybe something else? Should I add anything like decaps?
4. Is there any guidance on how to connect the pin of wrapper with the corresponding IO on pad?
Sorry for asking so many questions at a time.
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Amro Tork
07/06/2021, 11:48 AM@Shuo Lai and @Tim Edwards I would be interested to know how this end up.
Amro Tork
07/06/2021, 11:49 AM@Tim Edwards Just like Caravel, is there is a way to add analog simulation option target in the make flow that takes a spice netlist of the user_project_wrapper and run the simulation with all the IOs included?
Amro Tork
07/06/2021, 11:49 AMIs that doable?
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Tim Edwards
07/06/2021, 2:53 PMIt's doable, we just don't have any automatic make target for it.
Tim Edwards
07/06/2021, 3:07 PM@Shuo Lai:
(1) Assuming that VREG drivies a fairly high current, then use mprj_io[18:20]. The project wrapper cell shows only a metal3 pin (two pins, actually, because they are split around the clamp connections), but the caravan top level has a metal stack of metal3 + metal4 + metal5 at the boundary of the user wrapper. If you connect to the full metal stack, then you can drive several hundred mA through one pin.
(2) Yes, you can use chip_io_alt.spice as the model for the padframe. Make sure the SPICE file is more recent than the chip_io_alt.mag file in mag/ (chip_io is for caravel; chip_io_alt is for caravan).
(3) All pads except for the first 6 and last 2 GPIO pads can be used for analog. On caravan, the pads mprj_io[14:24] are bare analog pads (but be aware that they have no ESD protection).
(4) The GPIO connections are shown in the figure below.
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