Is your setup file correct?

.../netgen/sky130A_setup.tcl

Check your netgen output for error messages (ie. can't find file, etc.) Also, I recommend putting the layout netlist first and the schematic netlist second. From the setup file.

# NOTE:  In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.

Hi, What is the purpose of io_oeb in user_project_wrapper?

So in the std cells, the

nwell.pin

and

pwell.pin

are the connections from the

li

layer to the bulk (either the n-well or the p-substrate). I'm a bit surprised there is only 1 per cell though, I thought there would be a bunch equally spaced like the

mcon

between the

li

and

met1

carrying the power rails.

Maybe interesting: We have created an open-source analog circuit design course using Xschem and ngspice, as well as using CACE as simulation runner and Jupyter notebooks for circuit sizing using gm/Id method. All materials, examples, xschem circuits, etc. are open-source. You are welcome to provide feedback or additions (via GH PR). We are using IHP open-source PDK as pure 130nm CMOS node. https://iic-jku.github.io/analog-circuit-design/

Hi all. Im trying to run MC analysis across process. It is my understanding from reading the sky130.lib.spice that the "mm" corner does this. However, I dont see this in my results. For example, the below measures vth of a PMOS using the "tt_mm" / "ss_mm" / "ff_mm" / "sf_mm" / "fs_mm" and most importantly the "mm" corners. I get standard deviations of ~ 4mV for all corners apart from "mm" which gives me 0.3mV. I didnt expect this as when I group together the data from all corners (apart from "mm" corner data) and plot, I get 5 distributions as one would expect (as shown). In addition, I get a standard deviation of 33mV which again one would expect since that includes mismatch across process corners. From this I would have expected the "mm" corner to give a standard deviation of ~ 33mV. Am I missing something here or does the sky130.lib.spice file need to be updated? I see the "mm" corner settings in it are: .param MC_MM_SWITCH=0 .param MC_PR_SWITCH=1 MC_MM_SWITCH = 1 and MC_PR_SWITCH=0 for all corners apart from "mm" which makes sense since they dont want to model mismatch across process. Setting MC_MM_SWITCH = 0 and MC_PR_SWITCH=1 thus models process spread. Should we not have a corner with MC_MM_SWITCH = 1 and MC_PR_SWITCH=1 setting to model mismatch across process?

Hello, I am new to this and still learning. I am currently getting this error, where can I find more information on my error and how to solve it? I am just trying to run the flow for a very simple sv circuit. ``default_nettype none` module Circuit ( output var logic b, input var logic clk, input var logic enable, input var logic a ); always_ff @(posedge clk) if (enable) b <= a; else b <= 0; endmodule

[18:22:27] ERROR    Subprocess had a non-zero exit.                                                                                                                                                                                                                     step.py:1170

[182227] ERROR Last 10 line(s): step.py:1175 [INFO] Setting signal max routing layer to: met5 and clock max routing layer to met5. {*}-density 0.81875 -timing_driven -routability_driven -skip_io -pad_right 0 -pad_left 0 -init_wirelength_coef 0.25 [WARNING GPL-0150] -skip_io will disable timing driven mode. [WARNING GPL-0151] -skip_io will disable routability driven mode. [INFO GPL-0002] DBU: 1000 [INFO GPL-0003] SiteSize: 460 2720 [INFO GPL-0004] CoreAreaLxLy: 5520 10880 [INFO GPL-0005] CoreAreaUxUy: 12880 16320 [ERROR GPL-0120] instance 2 width is larger than core. Error: gpl.tcl, 69 GPL-0120 [182227] ERROR Full log file: 'runs/RUN_2024-03-18_18-22-24/18-openroad-globalplacementskipio/openroad-globalplacementskipio.log' step.py:1176 [182227] WARNING The following warnings were generated by the flow: flow.py:628 [182227] WARNING 'PNR_SDC_FILE' is not defined. Using generic fallback SDC for OpenROAD PnR steps. flow.py:629 'SIGNOFF_SDC_FILE' is not defined. Using generic fallback SDC for OpenROAD PnR steps. 'PL_TARGET_DENSITY_PCT' not explicitly set, using dynamically calculated target density: 81.87500… [182227] ERROR The following error was encountered while running the flow: main.py:152 Global Placement Skip IO: subprocess (1, ['openroad', '-exit', '-no_splash', '-metrics', '/home/pontus/repositories/pm32/runs/RUN_2024-03-18_18-22-24/18-openroad-globalplacementskipio/or_metrics_out.json', '/nix/store/jj7zqc4z6fg8plw8w86wpl589yapxwlz-python3-3.11.6-env/lib/python3.11/site-packages/openlane/scripts/openroad/gpl.tcl']) failed [182227] ERROR OpenLane will now quit.

Hi community, I have an interesting question for you. I have a schematic in xschem and the xschemrc file and I am able to simulate the schematic, now the question is, how can I run the simulation from a script in python? Theoretically what I done with the GUI, push "netlist" button and than "simulate", but how can I do this command? any example?

Hi, anyone know how can I simulate Phase Noise in ngspice ?

Hi, I am trying to simulate a basic nfet circuit however, I am not sure why nothing happens when I click the Simulate button. I am trying to do transient analysis however nothing happens. I have also attached the spice file. I think it should be importing the .lib file for sky130 transistor models but it is not doing so. I have to do that manually and run ngspice manually from the terminal to make it work.

What is current state of Verilog-A model support, OpenVAF, PSP model in ngspice etc. ? Background is that I would like to get ngspice simulation for IHPSG13G2 going on ARM64 (e.g. Raspberry Pi OS)