Hi, I was trying to compile the <sky130 64x512_8 SRAM> using `sram_compiler.py` and it gave me the f...

Harsh Khandeparkar

05/13/2024, 12:11 PM

Hi, I was trying to compile the sky130 64x512_8 SRAM using

sram_compiler.py

and it gave me the following error. I also set

netlist_only = True

. The error is not thrown for lower number of words (eg: 16, 32) but occurs for higher values such as 128, 256. Is this a configuration issue or is this a bug? If it is a config issue, perhaps the example file should be changed.

Copy code

DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.

Matthew Guthaus

05/13/2024, 3:29 PM

This is a bug that is still outstanding

Harsh Khandeparkar

05/13/2024, 3:29 PM

Any way to work around it?

Matthew Guthaus

05/13/2024, 3:30 PM

I'm not sure

Harsh Khandeparkar

05/13/2024, 3:30 PM

Is it a regression or do older versions also have the same issue?

Matthew Guthaus

05/13/2024, 3:30 PM

I'm not sure

👍 1

Matthew Guthaus

05/13/2024, 3:31 PM

It didn't happen at some time, but then you'll be missing updates

Matthew Guthaus

05/13/2024, 3:31 PM

If you find a fix, please submit a PR. (There is an open issue already I believe)

Harsh Khandeparkar

05/13/2024, 3:32 PM

https://github.com/VLSIDA/OpenRAM/issues/228 is it this one?

Matthew Guthaus

05/13/2024, 4:12 PM

yes

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